Thomas Ferrère
Title
Cited by
Cited by
Year
Efficient robust monitoring for STL
A Donzé, T Ferrere, O Maler
International Conference on Computer Aided Verification, 264-279, 2013
1632013
Timed pattern matching
D Ulus, T Ferrère, E Asarin, O Maler
International Conference on Formal Modeling and Analysis of Timed Systems …, 2014
522014
Online timed pattern matching using derivatives
D Ulus, T Ferrère, E Asarin, O Maler
International Conference on Tools and Algorithms for the Construction and …, 2016
392016
Trace diagnostics using temporal implicants
T Ferrère, O Maler, D Ničković
International Symposium on Automated Technology for Verification and …, 2015
262015
AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic
D Ničković, O Lebeltel, O Maler, T Ferrère, D Ulus
International Journal on Software Tools for Technology Transfer 22 (6), 741-758, 2020
232020
Measuring with timed patterns
T Ferrere, O Maler, D Ničković, D Ulus
International Conference on Computer Aided Verification, 322-337, 2015
222015
On the quantitative semantics of regular expressions over real-valued signals
A Bakhirkin, T Ferrère, O Maler, D Ulus
International Conference on Formal Modeling and Analysis of Timed Systems …, 2017
212017
Localizing faults in Simulink/Stateflow models with STL
E Bartocci, T Ferrère, N Manjunath, D Ničković
Proceedings of the 21st International Conference on Hybrid Systems …, 2018
162018
Efficient parametric identification for STL
A Bakhirkin, T Ferrère, O Maler
Proceedings of the 21st International Conference on Hybrid Systems …, 2018
162018
Interface-aware signal temporal logic
T Ferrère, D Nickovic, A Donzé, H Ito, J Kapinski
Proceedings of the 22nd ACM International Conference on Hybrid Systems …, 2019
122019
A theory of register monitors
T Ferrère, TA Henzinger, NE Saraç
Proceedings of the 33rd Annual ACM/IEEE Symposium on Logic in Computer …, 2018
72018
The first-order logic of signals: keynote
A Bakhirkin, T Ferrère, TA Henzinger, D Ničković
Proceedings of the International Conference on Embedded Software, 1-10, 2018
62018
Online timed pattern matching using automata
A Bakhirkin, T Ferrere, D Nickovic, O Maler, E Asarin
International Conference on Formal Modeling and Analysis of Timed Systems …, 2018
62018
The compound interest in relaxing punctuality
T Ferrère
International Symposium on Formal Methods, 147-164, 2018
42018
The First-Order Logic of Signals
A Bakhirkin, T Ferrere, T Henzinger, D Nickovic
32018
Assertions and measurements for mixed-signal simulation
T Ferrere
Ph. D. thesis, Université Grenoble-Alpes, France, 2016
32016
Shape Expressions for Specifying and Extracting Signal Features
D Ničković, X Qin, T Ferrère, C Mateis, J Deshmukh
International Conference on Runtime Verification, 292-309, 2019
22019
From real-time logic to timed automata
T Ferrère, O Maler, D Ničković, A Pnueli
Journal of the ACM (JACM) 66 (3), 1-31, 2019
22019
Mixed-Time Signal Temporal Logic
T Ferrère, O Maler, D Ničković
International Conference on Formal Modeling and Analysis of Timed Systems, 59-75, 2019
12019
Monitoring temporal logic with clock variables
A Elgyütt, T Ferrère, TA Henzinger
International Conference on Formal Modeling and Analysis of Timed Systems, 53-70, 2018
12018
The system can't perform the operation now. Try again later.
Articles 1–20