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Chun-Yao Wang
Chun-Yao Wang
Distinguished Professor of Computer Science, National Tsing Hua University
Verified email at cs.nthu.edu.tw - Homepage
Title
Cited by
Cited by
Year
Synthesis of reversible sequential elements
ML Chuang, CY Wang
ACM Journal on Emerging Technologies in Computing Systems (JETC) 3 (4), 1-19, 2008
1292008
Fast node merging with don't cares using logic implications
YC Chen, CY Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
312010
Fast detection of node mergers using logic implications
YC Chen, CY Wang
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
302009
Automated mapping for reconfigurable single-electron transistor arrays
YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan
Proceedings of the 48th Design Automation Conference, 878-883, 2011
282011
On automatic-verification pattern generation for SoC with port-order fault model
CY Wang, SW Tung, JY Jou
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
282002
LOOPLock: Logic optimization-based cyclic logic locking
HY Chiang, YC Chen, DX Ji, XM Yang, CC Lin, CY Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
262019
On rewiring and simplification for canonicity in threshold logic circuits
PY Kuo, CY Wang, CY Huang
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 396-403, 2011
262011
On synthesizing memristor-based logic circuits with minimal operational pulses
HP Wang, CC Lin, CC Wu, YC Chen, CY Wang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
252018
Node addition and removal in the presence of don't cares
YC Chen, CY Wang
Proceedings of the 47th Design Automation Conference, 505-510, 2010
212010
A synthesis algorithm for reconfigurable single-electron transistor arrays
YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (1), 1-20, 2013
202013
LOOPLock 2.0: An enhanced cyclic logic locking approach
XM Yang, PP Chen, HY Chiang, CC Lin, YC Chen, CY Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
192021
On reconfigurable single-electron transistor arrays synthesis using reordering techniques
CE Chiang, LF Tang, CY Wang, CY Huang, YC Chen, S Datta, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
192013
Rewiring for threshold logic circuit minimization
CC Lin, CY Wang, YC Chen, CY Huang
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
182014
A bus-encoding scheme for crosstalk elimination in high-performance processor design
WW Hsieh, PY Chen, CY Wang, TT Hwang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
172007
Majority logic circuits optimisation by node merging
CC Chung, YC Chen, CY Wang, CC Wu
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 714-719, 2017
162017
Logic Restructuring Using Node Addition and Removal
YC Chen, CY Wang
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2012
162012
Rewiring using irredundancy removal and addition
CC Lin, CY Wang
2009 Design, Automation & Test in Europe Conference & Exhibition, 324-327, 2009
162009
Verification of reconfigurable binary decision diagram-based single-electron transistor arrays
YC Chen, CY Wang, CY Huang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
142013
Synthesis and verification of cyclic combinational circuits
JH Chen, YC Chen, WC Weng, CY Huang, CY Wang
2015 28th IEEE International System-on-Chip Conference (SOCC), 257-262, 2015
132015
Width minimization in the single-electron transistor array synthesis
CW Liu, CE Chiang, CY Huang, CY Wang, YC Chen, S Datta, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
132014
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