| Integrating quick resource estimators in hardware construction framework for design space exploration B Ferres, O Muller, F Rousseau 2021 IEEE International Workshop on Rapid System Prototyping (RSP), 64-70, 2021 | 3 | 2021 |
| Chisel Usecase: Designing General Matrix Multiply for FPGA B Ferres, O Muller, F Rousseau Applied Reconfigurable Computing. Architectures, Tools, and Applications …, 2020 | 3 | 2020 |
| A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving O Oulkaid, B Ferres, M Moy, P Raymond, M Khosravian, L Henrio, ... 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | 2 | 2024 |
| A chisel framework for flexible design space exploration through a functional approach B Ferres, O Muller, F Rousseau ACM Transactions on Design Automation of Electronic Systems 28 (4), 1-31, 2023 | 1 | 2023 |
| Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory B Ferres, O Oulkaid, L Henrio, M Moy, G Radanne, P Raymond 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-2, 2023 | 1 | 2023 |
| [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler B Ferres | | 2030 |
| Leveraging Hardware Construction Languages for Flexible Design Space Exploration on FPGA B Ferres Université Grenoble Alpes, 2022 | | 2022 |
| Utilisation de langages de construction matérielle pour une exploration flexible des espaces de conception sur FPGA B Ferres | | 2022 |
| Computer Science Ph. D Proposal (CIFRE) Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level B Ferres, MK Ghadikolaei | | |
| Computer Science Ph. D Proposal (CIFRE) Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level B Ferres, MK Ghadikolaei | | |
Frederic Rousseauprofessor in computer science, Université Grenoble-AlpesAdresse e-mail validée de univ-grenoble-alpes.fr
