Generalized hyperbolic CORDIC and its logarithmic and exponential computation with arbitrary fixed base Y Luo, Y Wang, Y Ha, Z Wang, S Chen, H Pan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (9 …, 2019
45 2019 PLAC: Piecewise linear approximation computation for all nonlinear unary functions H Dong, M Wang, Y Luo, M Zheng, M An, Y Ha, H Pan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (9 …, 2020
44 2020 A universal method of linear approximation with controllable error for the efficient implementation of transcendental functions H Sun, Y Luo, Y Ha, Y Shi, Y Gao, Q Shen, H Pan
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (1), 177-188, 2019
38 2019 CORDIC-based architecture for computing Nth root and its implementation Y Luo, Y Wang, H Sun, Y Zha, Z Wang, H Pan
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4183-4195, 2018
32 2018 GH CORDIC-Based Architecture for Computing Y Wang, Y Luo, Z Wang, Q Shen, H Pan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4), 864-875, 2020
21 2020 Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing N th Roots of Floating-Point Numbers F Lyu, X Xu, Y Wang, Y Luo, Y Wang, H Pan
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 715-727, 2020
16 2020 A CORDIC-based architecture with adjustable precision and flexible scalability to implement sigmoid and tanh functions H Chen, L Jiang, Y Luo, Z Lu, Y Fu, L Li, Z Yu
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
11 2020 PWL-based architecture for the logarithmic computation of floating-point numbers F Lyu, Z Mao, J Zhang, Y Wang, Y Luo
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (7 …, 2021
8 2021 An optimized compression strategy for compressor-based approximate multiplier M Wang, Y Luo, M An, Y Qiu, M Zheng, Z Wang, H Pan
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
8 2020 ML-PLAC: Multiplierless piecewise linear approximation for nonlinear function evaluation F Lyu, Y Xia, Z Mao, Y Wang, Y Wang, Y Luo
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (4), 1546-1559, 2021
6 2021 High-throughput low-latency pipelined divider for single-precision floating-point numbers F Lyu, Y Xia, Y Chen, Y Wang, Y Luo, Y Wang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (4), 544-548, 2022
5 2022 Piecewise Parabolic Approximate Computation Based on an Error-Flattened Segmenter and a Novel Quantizer M An, Y Luo, M Zheng, Y Wang, H Dong, Z Wang, C Peng, H Pan
Electronics 10 (21), 2704, 2021
5 2021 A hidden DCT-based invisible watermarking method for low-cost hardware implementations Y Wang, Y Luo, Z Wang, H Pan
Electronics 10 (12), 1465, 2021
4 2021 Effective Plug-Ins for Reducing Inference-Latency of Spiking Convolutional Neural Networks During Inference Phase X Chen, X Yuan, G Fu, Y Luo, T Yue, F Yan, Y Wang, H Pan
Frontiers in Computational Neuroscience 15, 697469, 2021
2 2021 Corrections to “Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base”[Sep 19 Y Luo, Y Wang, Y Ha, Z Wang, S Chen, H Pan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (09 …, 2019
2 2019 An optimized hardware implementation of the CORDIC algorithm F Lyu, C Wu, Y Wang, H Pan, Y Wang, Y Luo
IEICE Electronics Express 19 (21), 20220362-20220362, 2022
1 2022 Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method F Lyu, J Chen, S Huang, W Wang, Y Luo, Y Wang
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2117-2121, 2022
1 2022 CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter M Zheng, Y Luo, H Pan, Z Wang, Y Xue
Journal of Signal Processing Systems 93, 617-629, 2021
1 2021 CLA Formula aided fast architecture design for clustered Look-Ahead pipelined IIR digital filter Y Luo, H Pan, Q Shen, Z Wang
2019 IEEE International Workshop on Signal Processing Systems (SiPS), 60-66, 2019
1 2019 FDM: Fused Double-Multiply Design for Low-Latency and Area-and Power-Efficient Implementation Y Wang, X Liang, S Niu, C Zhang, F Lyu, Y Luo
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
2023 
Zhongfeng WangNanjing UniversityAdresse e-mail validée de nju.edu.cn
