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Dax M. Crum
Dax M. Crum
Adresse e-mail validée de utexas.edu
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Année
Perpendicular reading of single confined magnetic skyrmions
DM Crum, M Bouhassoune, J Bouaziz, B Schweflinghaus, S Blügel, ...
Nature communications 6 (1), 1-8, 2015
992015
Methods for modeling non-equilibrium degenerate statistics and quantum-confined scattering in 3D ensemble Monte Carlo transport simulations
DM Crum, A Valsaraj, JK David, LF Register, SK Banerjee
Journal of Applied Physics 120 (22), 224301, 2016
72016
Semi-classical Monte Carlo study of the impact of contact geometry and transmissivity on quasi-ballistic nanoscale Si and In0.53Ga0.47As n-channel FinFETs
AA Bhatti, DM Crum, A Valsaraj, LF Register, SK Banerjee
Journal of Applied Physics 126 (10), 105705, 2019
22019
Impact of gate oxide complex band structure on n-channel III–V FinFETs
DM Crum, A Valsaraj, LF Register, SK Banerjee, B Sahu, Z Krivakopic, ...
2015 International Conference on Simulation of Semiconductor Processes and …, 2015
22015
Semi-classical ensemble Monte Carlo simulator using innovative quantum corrections for nano-scale n-channel FinFETs
DM Crum, A Valsaraj, LF Register, SK Banerjee
2014 International Conference on Simulation of Semiconductor Processes and …, 2014
22014
Monte Carlo Study of Si, Ge, and In0.53Ga0.47As n-Channel FinFET Scaling: Channel Orientation, Quantum Confinement, Doping, and Contacts
AA Bhatti, N Navlakha, DM Crum, SK Banerjee, LF Register
IEEE Nanotechnology Magazine 14 (6), 17-31, 2020
12020
Self-aligned gate endcap (sage) architectures with gate-all-around devices
B Guha, W Hsu, LP Guler, T Ghani
US Patent App. 17/549,827, 2022
2022
Fabrication of gate-all-around integrated circuit structures having additive metal gates
DS Lavric, O Saadat, O Golonzka, T Ghani
US Patent App. 17/031,832, 2022
2022
Fabrication of gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer
DS Lavric, O Golonzka, T Ghani
US Patent App. 17/030,346, 2022
2022
Fabrication of gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer
DS Lavric, O Saadat, O Golonzka, T Ghani
US Patent App. 17/030,333, 2022
2022
Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer
DG Ouellette, DB O'brien, O Acton, L BAUMGARTEL, DS Lavric, ...
US Patent App. 17/030,350, 2022
2022
Semi-Classical Monte Carlo Simulation of Contact Geometry, Orientation, and Ideality on Nano-scale Si and III-V n-channel FinFETs in the Quasi-Ballistic Limit
AA Bhatti, DM Crum, A Valsaraj, LF Register, SK Banerjee
arXiv preprint arXiv:1903.12281, 2019
2019
Ensemble Monte Carlo for III-V and Si n-channel FinFETs considering non-equilibrium degenerate statistics and quantum-confined scattering
DM Crum, A Valsaraj, JK David, LF Register, SK Banerjee
arXiv preprint arXiv:1604.00085, 2016
2016
Advanced modeling for end-of-the-roadmap CMOS and potential beyond-CMOS applications
DM Crum
2016
2020 Index IEEE Nanotechnology Magazine Vol. 14
M Abdelgawad, F Alnaimat, M Anantram, N Athreya, S Bandyopadhyay, ...
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