| Track assignment: A desirable intermediate step between global routing and detailed routing S Batterywala, N Shenoy, W Nicholls, H Zhou Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 100 | 2002 |
| A statistical method for fast and accurate capacitance extraction in the presence of floating dummy fills S Batterywala, R Ananthakrishna, Y Luo, A Gyure 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 37 | 2006 |
| Variance reduction in Monte Carlo capacitance extraction SH Batterywala, MP Desai 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 36 | 2005 |
| Method and apparatus for estimating parasitic capacitance SH Batterywala, N Shenoy, M Desai US Patent 7,260,797, 2007 | 19 | 2007 |
| Legalizing a portion of a circuit layout SH Batterywala, S Bhattacharya, S Rajagopalan, HKT Ma US Patent 9,043,741, 2015 | 18 | 2015 |
| Legalizing a multi-patterning integrated circuit layout S Bhattacharya, S Rajagopalan, SH Batterywala US Patent 9,904,755, 2018 | 15 | 2018 |
| Method and apparatus for computing equivalent capacitance SH Batterywala US Patent 7,197,729, 2007 | 15 | 2007 |
| Efficient DC analysis of RVJ circuits for moment and derivative computations of interconnect networks SH Batterywala, H Narayanan Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999 | 14 | 1999 |
| Impact of modern process technologies on the electrical parameters of interconnects D Sinha, J Luo, S Rajagopalan, S Batterywala, NV Shenoy, H Zhou 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 13 | 2007 |
| Cell swapping based migration methodology for analog and custom layouts SH Batterywala, S Bhattacharya, S Rajagopalan, HKT Ma, NV Shenoy 9th International Symposium on Quality Electronic Design (isqed 2008), 450-455, 2008 | 12 | 2008 |
| Automatic layout modification tool with non-uniform grids ND Salodkar, S Rajagopalan, S Bhattacharya, SH Batterywala US Patent 9,898,567, 2018 | 9 | 2018 |
| A 3-dimensional FEM based resistance extraction S Rajagopalan, S Batterywala 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 6 | 2007 |
| Parallelizing a statistical capacitance extractor N Sawhney, S Batterywala, N Shenoy, R Rudell Proceedings of VLSI design and test, 253-267, 2004 | 6 | 2004 |
| A method to estimate slew and delay in coupled digital circuits S Batterywala, N Shenoy 16th International Conference on VLSI Design, 2003. Proceedings., 411-416, 2003 | 5 | 2003 |
| On efficient and robust constraint generation for practical layout legalization S Bhattacharya, SH Batterywala, S Rajagopalan, HKT Ma, NV Shenoy 9th International Symposium on Quality Electronic Design (isqed 2008), 379-384, 2008 | 3 | 2008 |
| MoM-a process variation aware statistical capacitance extractor R Ananthakrishna, S Batterywala 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 3 | 2006 |
| Fixing Double Patterning violations with look-ahead S Bhattacharya, S Rajagopalan, SH Batterywala 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 149-154, 2014 | 2 | 2014 |
| Time domain method for reduced order network synthesis of large RC circuits SH Batterywala, H Narayanan ISCAS'98. Proceedings of the 1998 IEEE International Symposium on Circuits …, 1998 | 2 | 1998 |
| Automatic design rule correction in presence of multiple grids and track patterns N Salodkar, S Rajagopalan, S Bhattacharya, S Batterywala Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 1 | 2013 |
| Efficient analog/rf layout closure with compaction based legalization S Rajagopalan, S Bhattacharya, SH Batterywala 2009 22nd International Conference on VLSI Design, 137-142, 2009 | 1 | 2009 |
