Ney Laert Vilar Calazans
Ney Laert Vilar Calazans
Invited Researcher at the Graduate Program on Microelectronics (PGMICRO), UFRGS
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HERMES: an infrastructure for low area overhead packet-switching networks on chip
F Moraes, N Calazans, A Mello, L Möller, L Ost
Integration 38 (1), 69-93, 2004
Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs
E Carvalho, N Calazans, F Moraes
18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP'07 …, 2007
Dynamic task mapping for MPSoCs
EL de Souza Carvalho, NLV Calazans, FG Moraes
IEEE Design & Test of Computers 27 (5), 26-35, 2010
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
A Mello, L Tedesco, N Calazans, F Moraes
Proceedings of the 18th annual symposium on Integrated circuits and system …, 2005
HeMPS-a framework for NoC-based MPSoC generation
EA Carara, RP de Oliveira, NLV Calazans, FG Moraes
2009 IEEE International Symposium on Circuits and Systems, 1345-1348, 2009
Exploring NoC mapping strategies: an energy and timing aware technique
C Marcon, N Calazans, F Moraes, A Susin, I Reis, F Hessel
Design, Automation and Test in Europe, 502-507, 2005
MAIA: a framework for networks on chip generation and verification
L Ost, A Mello, J Palma, F Moraes, N Calazans
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses
NLV Calazans, FG Moraes
IEEE Transactions on Education 44 (2), 109-119, 2001
Remote and Partial Reconfiguration of FPGAs: tools and trends
D Mesquita, F Moraes, J Palma, L Moller, N Calazans
Proceedings International Parallel and Distributed Processing Symposium, 8 pp., 2003
Evaluation of routing algorithms on mesh based nocs
AV de Mello, LC Ost, FG Moraes, NLV Calazans
PUCRS, Av. Ipiranga 22, 2004
Comparison of network-on-chip mapping algorithms targeting low energy consumption
CAM Marcon, EI Moreno, NLV Calazans, FG Moraes
IET Computers & Digital Techniques 2 (6), 471-482, 2008
Blade--a timing violation resilient asynchronous template
D Hand, MT Moreira, HH Huang, D Chen, F Butzke, Z Li, M Gibiluka, ...
2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.
FG Moraes, A Mello, L Möller, L Ost, NLV Calazans
VLSI-SOC, 318-323, 2003
Traffic generation and performance evaluation for mesh-based NoCs
L Tedesco, A Mello, D Garibotti, N Calazans, F Moraes
Proceedings of the 18th annual symposium on Integrated circuits and system …, 2005
From VHDL register transfer level to SystemC transaction level modeling: a comparative case study
N Calazans, E Moreno, F Hessel, V Rosa, F Moraes, E Carara
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
NoC power estimation at the RTL abstraction level
G Guindani, C Reinbrecht, T Raupp, N Calazans, FG Moraes
2008 IEEE Computer Society Annual Symposium on VLSI, 475-478, 2008
Core communication interface for FPGAs
JC Palma, AV de Mello, L Moller, F Moraes, N Calazans
Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 183-188, 2002
PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems
E Carvalho, N Calazans, E Brião, F Moraes
Proceedings of the 17th symposium on Integrated circuits and system design …, 2004
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes
MT Moreira, RA Guazzelli, NLV Calazans
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012
Impact of C-elements in asynchronous circuits
M Moreira, B Oliveira, F Moraes, N Calazans
Thirteenth International Symposium on Quality Electronic Design (ISQED), 437-343, 2012
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