Nihar Ranjan Mohapatra
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The effect of high-k gate dielectrics on deep submicrometer CMOS device and circuit performance
NR Mohapatra, MP Desai, SG Narendra, VR Rao
IEEE transactions on electron devices 49 (5), 826-831, 2002
Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors
NR Mohapatra, MP Desai, SG Narendra, VR Rao
IEEE Transactions on Electron devices 50 (4), 959-966, 2003
Leaky integrate and fire neuron by charge-discharge dynamics in floating-body MOSFET
S Dutta, V Kumar, A Shukla, NR Mohapatra, U Ganguly
Scientific reports 7 (1), 1-7, 2017
Soi transistor with floating body for information storage having asymmetric drain/source regions
R Van Bentum, NR Mohapatra
US Patent App. 12/353,431, 2009
32nm high-density high-speed T-RAM embedded memory technology
R Gupta, F Nemati, S Robins, K Yang, V Gopalakrishnan, JJ Sundarraj, ...
2010 International Electron Devices Meeting, 12.1. 1-12.1. 4, 2010
A complementary RF-LDMOS architecture compatible with 0.13 μm CMOS technology
NR Mohapatra, H Ruecker, KE Ehwald, R Sorge, R Barth, P Schley, ...
2006 IEEE International Symposium on Power Semiconductor Devices and IC's, 1-4, 2006
Integration of high-performance SiGe: C HBTs with thin-film SOI CMOS
H Rucker, B Heinemann, R Barth, D Bolze, J Drews, O Fursenko, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters
NR Mohapatra, DR Nair, S Mahapatra, VR Rao, S Shukuri, JD Bude
IEEE Transactions on Electron Devices 50 (10), 2104-2111, 2003
Modeling of quantum confinement and capacitance in III–V gate-all-around 1-D transistors
MD Ganeriwala, C Yadav, FG Ruiz, EG Marin, YS Chauhan, ...
IEEE Transactions on Electron Devices 64 (12), 4889-4896, 2017
Modeling of charge and quantum capacitance in low effective mass III-V FinFETs
MD Ganeriwala, C Yadav, NR Mohapatra, S Khandelwal, C Hu, ...
IEEE Journal of the Electron Devices Society 4 (6), 396-401, 2016
Fast and accurate lithography simulation using cluster analysis in resist model building
P Kumar, B Srinivasan, NR Mohapatra
Journal of Micro/Nanolithography, MEMS, and MOEMS 14 (2), 023506, 2015
Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics
NR Mohapatra, MP Desai, VR Rao
16th International Conference on VLSI Design, 2003. Proceedings., 99-104, 2003
The impact of channel engineering on the performance and reliability of LDMOS transistors
NR Mohapatra, KE Ehwald, R Barth, H Rucker, D Bolze, P Schley, ...
Proceedings of 35th European Solid-State Device Research Conference, 2005 …, 2005
Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs
NR Mohapatra, S Mahapatra, VR Rao, S Shukuri, J Bude
2003 IEEE International Reliability Physics Symposium Proceedings, 2003 …, 2003
Memory unit with bit line discharger
VW Chang, H Katircioglu, H Kumar, N Mohapatra
US Patent 5,627,788, 1997
Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics
NR Mohapatra, A Dutta, MP Desai, VR Rao
VLSI Design 2001. Fourteenth International Conference on VLSI Design, 479-482, 2001
Band-to-band tunneling based ultra-energy-efficient silicon neuron
T Chavan, S Dutta, NR Mohapatra, U Ganguly
IEEE Transactions on Electron Devices 67 (6), 2614-2620, 2020
Variability sources in nanoscale bulk FinFETs and TiTaN-a promising low variability WFM for 7/5nm CMOS nodes
MS Bhoir, T Chiarella, LÅ Ragnarsson, J Mitard, N Horiguchi, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.2. 1-36.2. 4, 2019
Transient variability in SOI-based LIF neuron and impact on unsupervised learning
S Dutta, T Bhattacharya, NR Mohapatra, M Suri, U Ganguly
IEEE Transactions on Electron Devices 65 (11), 5137-5144, 2018
A compact charge and surface potential model for III–V cylindrical nanowire transistors
MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
IEEE Transactions on Electron Devices 66 (1), 73-79, 2018
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