| A zero-cost technique to improve ON-state performance and reliability of power LDMOS transistors KN Kaushal, NR Mohapatra IEEE Journal of the Electron Devices Society 9, 334-341, 2021 | 10 | 2021 |
| Source Underlap—A Novel Technique to Improve Safe Operating Area and Output-Conductance in LDMOS Transistors MS Bhoir, KN Kaushal, SR Panda, AK Singh, HS Jatana, NR Mohapatra IEEE Transactions on Electron Devices 66 (11), 4823-4828, 2019 | 10 | 2019 |
| Unified theory of the capacitance behavior in LDMOS devices KN Kaushal, NR Mohapatra IEEE Transactions on Electron Devices 69 (1), 39-44, 2021 | 8 | 2021 |
| Scalable substrate current model for LDMOS transistors based on internal drain voltage KN Kaushal, V Dan, NR Mohapatra IEEE Transactions on Electron Devices 69 (8), 4095-4101, 2022 | 5 | 2022 |
| A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors KN Kaushal, NR Mohapatra IEEE Transactions on Electron Devices 70 (3), 857-863, 2023 | 3 | 2023 |
| Behavior of LDMOS transistors at cryogenic temperature-An experiment based analysis KK Neeraj, MN Ranjan 2021 25th International Symposium on VLSI Design and Test (VDAT), 1-4, 2021 | 3 | 2021 |
| Compact Modeling of LDMOS Transistors Over a Wide Temperature Range Including Cryogenics Y Machhiwar, G Gill, KN Kaushal, NR Mohapatra, H Agarwal IEEE Transactions on Electron Devices, 2023 | | 2023 |
| Physics-based parameter extraction methodology for channel doping gradient (CDG) LDMOS transistors based on HiSIM-HV2 model S Patil, KN Kaushal, MS Bhoir, NR Mohapatra 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2021 | | 2021 |
