Jean-Christophe Le Lann
Jean-Christophe Le Lann
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Cited by
Cited by
Polychrony for system design
P Le Guernic, JP Talpin, JC Le Lann
Journal of Circuits, Systems, and Computers 12 (03), 261-303, 2003
Using MARTE in a co-design methodology
A Koudri, D Aulagnier, D Vojtisek, P Soulard, C Moy, J Champeau, J Vidal, ...
Extended overlay architectures for heterogeneous FPGA cluster management
M Najem, T Bollengier, JC Le Lann, L Lagadec
Journal of Systems Architecture 78, 1-14, 2017
Mhpm: Multi-scale hybrid programming model: A flexible parallelization methodology
N Khammassi, JC Le Lann, JP Diguet, A Skrzyniarz
2012 IEEE 14th International Conference on High Performance Computing and …, 2012
Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging
L Lagadec, C Teodorov, JC Le Lann, D Picard, E Fabiani
Science of Computer Programming 96, 156-174, 2014
Mopcom methodology: Focus on models of computation
A Koudri, J Champeau, JC Le Lann, V Leilde
European Conference on Modelling Foundations and Applications, 189-200, 2010
Cardin: An agile environment for edge computing on reconfigurable sensor networks
XS Le, JC Le Lann, L Lagadec, L Fabresse, N Bouraqadi, J Laval
2016 International Conference on Computational Science and Computational …, 2016
A prototyping platform for virtual reconfigurable units
L Lagadec, JC Le Lann, T Bollengier
2014 9th International Symposium on Reconfigurable and Communication-Centric …, 2014
A cost-effective approach for efficient time-sharing of reconfigurable architectures
M Najem, T Bollengier, JC Le Lann, L Lagadec
2017 International Conference on FPGA Reconfiguration for General-Purpose …, 2017
Soft timing closure for soft programmable logic cores: The ARGen approach
T Bollengier, L Lagadec, M Najem, JC Le Lann, P Guilloux
International Symposium on Applied Reconfigurable Computing, 93-105, 2017
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC
J Heulot, K Desnos, JF Nezan, M Pelcat, M Raulet, H Yviquel, ...
Proceedings of the 2012 Conference on Design and Architectures for Signal …, 2012
Simulation et synthèse de circuits s' appuyant sur le modèle synchrone
JC Le Lann
Rennes 1, 2002
High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system
AA Kountouris, C Wolinski, JC Le Lann
Journal of systems architecture 47 (3-4), 293-313, 2001
A synchronous approach for hardware design
M Allemand, F Bodin, A Kountouris, P Le Guernic, JC Le Lann, A Seznec, ...
IRISA, 1997
Overlay architectures for heterogeneous FPGA cluster management
T Bollengier, M Najem, JC Le Lann, L Lagadec
2016 Conference on Design and Architectures for Signal and Image Processing …, 2016
Overlay architectures for fpga resource virtualization
T Bollengier, M Najem, JC Le Lann, L Lagadec
A high-level programming model to ease pipeline parallelism expression on shared memory multicore architectures
N Khammassi, JC Le Lann
Proceedings of the High Performance Computing Symposium, 1-8, 2014
Design and implementation of a cache hierarchy-aware task scheduling for parallel loops on multicore architectures
N Khammassi, JC Le Lann
PDCTA, Sydney, Australia, 2014
Arithmetic decoding method and device
JC Le Lann, C Jollivet, G Cocherel, M Fossard
US Patent 7,876,240, 2011
Video Encoding Analysis for Parallel Execution on Reconfigurable Architectures
M Rashid, JC Le Lann, K Bertels
6th Symposium on Design, Analysis and Simulation of Distributed Systems, 2008
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