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Guénolé Lallement
Guénolé Lallement
Lead Physical Design Engineer, Efficient AI
Adresse e-mail validée de efficient.computer - Page d'accueil
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CHIMERA: A 0.92 TOPS, 2.2 TOPS/W edge AI accelerator with 2 MByte on-chip foundry resistive RAM for efficient training and inference
M Giordano, K Prabhu, K Koul, RM Radway, A Gural, R Doshi, ZF Khan, ...
2021 symposium on VLSI circuits, 1-2, 2021
482021
A 2.7 pJ/cycle 16 MHz, 0.7 μW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI
G Lallement, F Abouzeid, M Cochet, JM Daveau, P Roche, JL Autran
IEEE Journal of Solid-State Circuits, 2018
322018
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W edge AI accelerator with 2-MByte on-chip foundry resistive RAM for efficient training and inference
K Prabhu, A Gural, ZF Khan, RM Radway, M Giordano, K Koul, R Doshi, ...
IEEE Journal of Solid-State Circuits 57 (4), 1013-1026, 2022
262022
Q-learning-based adaptive power management for IoT system-on-chips with embedded power states
Y Debizet, G Lallement, F Abouzeid, P Roche, JL Autran
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
182018
A 2.7 pJ/cycle 16MHz SoC with 4.3 nW power-off ARM Cortex-M0+ core in 28nm FD-SOI
G Lallement, F Abouzeid, M Cochet, JM Daveau, P Roche, JL Autran
ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 153-162, 2017
162017
A 1.1-pJ/cycle, 20-MHz, 0.42-V temperature compensated ARM Cortex-M0+ SoC with adaptive self body-biasing in FD-SOI
G Lallement, F Abouzeid, JM Daveau, P Roche, JL Autran
IEEE Solid-State Circuits Letters 1 (7), 174-177, 2018
142018
On-chip total ionizing dose digital monitor in fully depleted SOI technologies
F Abouzeid, G Gasiot, D Soussan, CLM de Boissac, V Malherbe, V Bertin, ...
IEEE Transactions on Nuclear Science 67 (7), 1326-1331, 2020
82020
Bio-inspired pH sensing using ion sensitive field effect transistors
G Lallement, N Moser, P Georgiou
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2835-2838, 2016
42016
A 0.40pJ/cycle 981 μm2voltage scalable digital frequency generator for SoC clocking
M Cochet, S Clerc, G Lallement, F Abouzeid, P Roche, JL Autran
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 69-72, 2017
22017
Extension of SoCs mission capabilities by offering near-zero-power performances and enabling continuous functionality for IoT systems
G Lallement
Aix-Marseille, 2019
12019
Low power circuits for emerging applications in communications, computing, and sensing
F Yuan
CRC Press, 2018
12018
Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices
LR Upton, G Lallement, MD Scott, J Taylor, RM Radway, D Rich, ...
2023 24th International Symposium on Quality Electronic Design (ISQED), 1-7, 2023
2023
Body biasing for ultra-low voltage digital circuits
G Lallement, F Abouzeid
US Patent 10,739,807, 2020
2020
Leakage-based oscillator with digital correction
G Lallement, F Abouzeid
US Patent 10,469,058, 2019
2019
Clock Generation and Distribution for Low-Power Digital Systems
M Cochet, G Lallement, F Abouzeid, P Roche
Low Power Circuits for Emerging Applications in Communications, Computing …, 2018
2018
A 140 nW, 32.768 kHz, 1.9 ppm/° C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI
G Lallement, F Abouzeid, T Di Gilio, P Roche, JL Autran
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 197-200, 2018
2018
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