Francesca Palumbo
Francesca Palumbo
UNISS - Università degli Studi di Sassari
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An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks
D Pani, P Meloni, G Tuveri, F Palumbo, P Massobrio, L Raffo
Frontiers in neuroscience 11, 90, 2017
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms
F Palumbo, N Carta, D Pani, P Meloni, L Raffo
Journal of real-time image processing 9 (1), 233-249, 2014
Power-awarness in coarse-grained reconfigurable multi-functional architectures: a dataflow based strategy
F Palumbo, T Fanni, C Sau, P Meloni
Journal of Signal Processing Systems 87 (1), 81-106, 2017
Cross-layer design of reconfigurable cyber-physical systems
M Masin, F Palumbo, H Myrhaug, JA de Oliveira Filho, M Pastena, ...
2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 740-745, 2017
The multi-dataflow composer tool: A runtime reconfigurable hdl platform composer
F Palumbo, N Carta, L Raffo
Proceedings of the 2011 Conference on Design & Architectures for Signal …, 2011
Automated Design Flow for Multi-Functional Dataflow-Based Platforms
C Sau, P Meloni, L Raffo, F Palumbo, E Bezati, S Casale-Brunet, ...
Journal of Signal Processing Systems 85 (1), 143-165, 2016
Reconfigurable coprocessors synthesis in the MPEG-RVC domain
C Sau, L Fanni, P Meloni, L Raffo, F Palumbo
ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference …, 2015
RVC: A multi-decoder CAL Composer tool
F Palumbo, D Pani, E Manca, L Raffo, M Mattavelli, G Roquier
2010 Conference on Design and Architectures for Signal and Image Processing …, 2010
Coarse-grained reconfiguration: dataflow-based power management
F Palumbo, C Sau, L Raffo
Computers & Digital Techniques, IET 9 (1), 36-48, 2015
A coarse-grained reconfigurable approach for low-power spike sorting architectures
N Carta, C Sau, D Pani, F Palumbo, L Raffo
Neural Engineering (NER), 2013 6th International IEEE/EMBS Conference on …, 2013
A coarse-grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow Composer tool
N Carta, C Sau, F Palumbo, D Pani, L Raffo
Design and Architectures for Signal and Image Processing (DASIP), 2013 …, 2013
Power and clock gating modelling in coarse grained reconfigurable systems
T Fanni, C Sau, P Meloni, L Raffo, F Palumbo
Proceedings of the ACM International Conference on Computing Frontiers, 384-391, 2016
An integrated hardware/software design methodology for signal processing systems
L Li, C Sau, T Fanni, J Li, T Viitanen, F Christophe, F Palumbo, L Raffo, ...
Journal of Systems Architecture 93, 1-19, 2019
DSE and profiling of multi-context coarse-grained reconfigurable systems
F Palumbo, C Sau, L Raffo
Image and Signal Processing and Analysis (ISPA), 2013 8th International …, 2013
Introduction to the Tiled HW Architecture of SHAPES
PS Paolucci, F Lo Cicero, A Lonardo, M Perra, D Rossetti, C Sidore, ...
DATE 2007 Conference, France, Nice, 2007
Introduction to the Tiled HW Architecture of SHAPES
S PAOLUCCI P, F LO CICERO, A Lonardo, M Perra, D Rossetti, C Sidore, ...
DATE 2007 Friday Workshop, 79-82, 2007
Multi-purpose systems: A novel dataflow-based generation and mapping strategy
JF Nezan, N Siret, M Wipliez, F Palumbo, L Raffo
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, 3073-3076, 2012
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
C Sau, F Palumbo, M Pelcat, J Heulot, E Nogues, D Menard, P Meloni, ...
IEEE Embedded Systems Letters 9 (3), 65-68, 2017
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
C Sau, L Raffo, F Palumbo, E Bezati, S Casale-Brunet, M Mattavelli
2014 International Conference on Embedded Computer Systems: Architectures …, 2014
Design IP Faster: Introducing the CHigh-Level Language
M Wipliez, N Siret, N Carta, F Palumbo, L Raffo
Design & Reuse, 2013
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