| The Stratix II logic and routing architecture D Lewis, E Ahmed, G Baeckler, V Betz, M Bourgeault, D Cashman, ... Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field …, 2005 | 262 | 2005 |
| Physical resynthesis of a logic design MD Hutton, J Pistorius, B Van Antwerpen, G Baeckler, R Yuan, YY Hwang US Patent 7,337,100, 2008 | 106 | 2008 |
| Register retiming technique B Van Antwerpen, MD Hutton, G Baeckler, R Yuan US Patent 7,120,883, 2006 | 100 | 2006 |
| Improving FPGA performance and area using an adaptive logic module M Hutton, J Schleicher, D Lewis, B Pedersen, R Yuan, S Kaptanoglu, ... International Conference on Field Programmable Logic and Applications, 135-144, 2004 | 87 | 2004 |
| Efficient SAT-based Boolean matching for FPGA technology mapping S Safarpour, A Veneris, G Baeckler, R Yuan Proceedings of the 43rd Annual Design Automation Conference, 466-471, 2006 | 61 | 2006 |
| Logic cell supporting addition of three binary words G Baeckler, M Langhammer, J Schleicher, R Yuan US Patent 7,565,388, 2009 | 39 | 2009 |
| The stratix logic and routing architecture D Lewis, E Ahmed, G Baeckler, V Betz, M Bourgeault Proc FPGA-02, 12-20, 2002 | 37 | 2002 |
| A methodology for FPGA to structured-ASIC synthesis and verification M Hutton, R Yuan, J Schleicher, G Baeckler, S Cheung, KK Chua, ... Proceedings of the Design Automation & Test in Europe Conference 2, 1-6, 2006 | 30 | 2006 |
| High density and performance multiplication for FPGA M Langhammer, G Baeckler 2018 IEEE 25th Symposium on Computer Arithmetic (ARITH), 5-12, 2018 | 28 | 2018 |
| Omnibus logic element including look up table based logic elements J Schleicher, R Yuan, B Pedersen, S Kaptanoglu, G Baeckler, D Lewis, ... US Patent 7,167,022, 2007 | 26 | 2007 |
| Extracting INT8 multipliers from INT18 multipliers M Langhammer, B Pasca, G Baeckler, S Gribok 2019 29th International Conference on Field Programmable Logic and …, 2019 | 24 | 2019 |
| Register retiming technique B Van Antwerpen, MD Hutton, G Baeckler, R Yuan US Patent 7,689,955, 2010 | 24 | 2010 |
| Omnibus logic element J Schleicher, R Yuan, B Pedersen, S Kaptanoglu, G Baeckler, D Lewis, ... US Patent 7,538,579, 2009 | 20 | 2009 |
| Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage T Borer, I Chesal, J Schleicher, D Mendel, M Hutton, B Ratchev, Y Sankar, ... US Patent 7,181,703, 2007 | 17 | 2007 |
| Fast method for functional mapping to incomplete LUT pairs GW Baeckler, B Van Antwerpen US Patent 7,224,183, 2007 | 16 | 2007 |
| Register retiming technique B Van Antwerpen, MD Hutton, G Baeckler, R Yuan US Patent 8,402,408, 2013 | 15 | 2013 |
| Hardware acceleration of functional factoring GW Baeckler US Patent 7,640,528, 2009 | 13 | 2009 |
| High density 8-bit multiplier systolic arrays for FPGA M Langhammer, S Gribok, G Baeckler 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020 | 12 | 2020 |
| First-in first-out circuits and methods GW Baeckler, DW Mendel US Patent 9,330,740, 2016 | 12 | 2016 |
| Heterogeneous labs MD Hutton, K Duwel, GW Baeckler US Patent 7,902,864, 2011 | 12 | 2011 |
