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Mathieu Moreau
Mathieu Moreau
Associate professor, Aix-Marseille université, IM2NP
Adresse e-mail validée de im2np.fr
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Synchronous non-volatile logic gate design based on resistive switching memories
W Zhao, M Moreau, E Deng, Y Zhang, JM Portal, JO Klein, M Bocquet, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (2), 443-454, 2014
1162014
An overview of non-volatile flip-flops based on emerging memory technologies
JM Portal, M Bocquet, M Moreau, H Aziza, D Deleruyelle, Y Zhang, ...
Journal of Electronic Science and Technology 12 (2), 173-181, 2014
382014
RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications
H Bazzi, A Harb, H Aziza, M Moreau, A Kassem
Analog Integrated Circuits and Signal Processing 106 (2), 351-361, 2021
372021
True random number generator integration in a resistive RAM memory array using input current limitation
H Aziza, J Postel-Pellerin, H Bazzi, P Canet, M Moreau, V Della Marca, ...
IEEE Transactions on Nanotechnology 19, 214-222, 2020
372020
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures
A Levisse, B Giraud, JP Noël, M Moreau, JM Portal
Non-Volatile Memory Technology Symposium (NVMTS), 2015 15th, 1-4, 2015
342015
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells
WS Zhao, JM Portal, W Kang, M Moreau, Y Zhang, H Aziza, JO Klein, ...
Journal of Parallel and Distributed Computing 74 (6), 2484-2496, 2014
302014
Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2)/28 nm FDSOI CMOS Technology
JM Portal, M Bocquet, S Onkaraiah, M Moreau, H Aziza, D Deleruyelle, ...
IEEE Transactions on Nanotechnology 16 (4), 677-686, 2017
292017
Architecture, design and technology guidelines for crosspoint memories
A Levisse, B Giraud, JP Noel, M Moreau, JM Portal
2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2017
192017
Investigation of capacitance–voltage characteristics in Ge/high-κ MOS devices
M Moreau, D Munteanu, JL Autran, F Bellenger, J Mitard, M Houssa
Journal of Non-Crystalline Solids 355 (18-21), 1171-1175, 2009
182009
ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology
H Aziza, P Canet, J Postel-Pellerin, M Moreau, JM Portal, M Bocquet
2017 Joint International EUROSOI Workshop and International Conference on …, 2017
172017
True random number generation exploiting SET voltage variability in resistive RAM memory arrays
J Postel-Pellerin, H Bazzi, H Aziza, P Canet, M Moreau, V Della Marca, ...
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 1-5, 2019
152019
An Energy-Efficient Current-Controlled Write and Read Scheme for Resistive RAMs (RRAMs)
H Aziza, M Moreau, M Fieback, M Taouil, S Hamdioui
IEEE Access 8, 137263-137274, 2020
142020
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations
A Levisse, M Bocquet, M Rios, M Alayan, M Moreau, E Nowak, G Molas, ...
IEEE Access 8, 109297-109308, 2020
142020
Simulation analysis of quantum confinement and short-channel effects in independent double-gate metal–oxide–semiconductor field-effect transistors
M Moreau, D Munteanu, JL Autran
Japanese Journal of Applied Physics 47 (9R), 7013, 2008
142008
Multi-level control of resistive ram (Rram) using a write termination to achieve 4 bits/cell in high resistance state
H Aziza, S Hamdioui, M Fieback, M Taouil, M Moreau, P Girard, A Virazel, ...
Electronics 10 (18), 2222, 2021
132021
Switching event detection and self-termination programming circuit for energy efficient ReRAM memory arrays
M Alayan, E Muhr, A Levisse, M Bocquet, M Moreau, E Nowak, G Molas, ...
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (5), 748-752, 2019
122019
Simulation study of Short-Channel Effects and quantum confinement in double-gate FinFET devices with high-mobility materials
M Moreau, D Munteanu, JL Autran
Microelectronic engineering 88 (4), 366-369, 2011
112011
A capacitor-less CMOS neuron circuit for neuromemristive networks
H Aziza, M Moreau, A Perez, A Virazel, P Girard
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2019
102019
High density emerging resistive memories: What are the limits?
A Levisse, B Giraud, JP Noel, M Moreau, JM Portal
2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017
102017
Multilevel operation in oxide based resistive RAM with SET voltage modulation
H Aziza, H Ayari, S Onkaraiah, M Moreau, JM Portal, M Bocquet
2016 International Conference on Design and Technology of Integrated Systems …, 2016
102016
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