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Seng-Pan U (Ben), IEEE Fellow
Seng-Pan U (Ben), IEEE Fellow
University of Macau & Synopsys Macau Ltd.
Verified email at ieee.org - Homepage
Title
Cited by
Cited by
Year
A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS
Y Zhu, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Journal of Solid-state circuits 45 (6), 1111-1121, 2010
6042010
Transceiver architecture selection–review, state-of-the-art survey and case study
PI Mak, SP U, RP Martins
Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage …, 2007
2062007
A fully integrated digital LDO with coarse–fine-tuning and burst-mode operation
M Huang, Y Lu, SW Sin, U Seng-Pan, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (7), 683-687, 2016
1282016
A wide input range dual-path CMOS rectifier for RF energy harvesting
Y Lu, H Dai, M Huang, MK Law, SW Sin, U Seng-Pan, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (2), 166-170, 2016
1242016
An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC
H Wei, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Journal of Solid-State Circuits 47 (11), 2763-2772, 2012
1002012
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS
H Wei, CH Chan, UF Chio, SW Sin, U Seng-Pan, R Martins, F Maloberti
2011 IEEE International Solid-State Circuits Conference, 188-190, 2011
892011
An analog-assisted tri-loop digital low-dropout regulator
M Huang, Y Lu, U Seng-Pan, RP Martins
IEEE Journal of Solid-State Circuits 53 (1), 20-34, 2017
842017
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
CH Chan, Y Zhu, UF Chio, SW Sin, U Seng-Pan, RP Martins
IEEE Asian Solid-State Circuits Conference 2011, 233-236, 2011
742011
On the design of a programmable-gain amplifier with built-in compact DC-offset cancellers for very low-voltage WLAN systems
PI Mak, U Seng-Pan, RP Martins
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (2), 496-509, 2008
742008
A 3.8 mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
CH Chan, Y Zhu, SW Sin, U Seng-Pan, RP Martins
2012 Symposium on VLSI Circuits (VLSIC), 86-87, 2012
702012
20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control
M Huang, Y Lu, U Seng-Pan, RP Martins
2017 IEEE International Solid-State Circuits Conference (ISSCC), 342-343, 2017
692017
Split-SAR ADCs: Improved linearity with power and speed optimization
Y Zhu, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (2), 372-383, 2013
672013
Enhanced hydrogen generation by hydrolysis of Mg doped with flower-like MoS2 for fuel cell applications
M Huang, L Ouyang, J Liu, H Wang, H Shao, M Zhu
Journal of Power Sources 365, 273-281, 2017
622017
26.5 A 5.5 mW 6b 5GS/S 4ื-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
CH Chan, Y Zhu, SW Sin, U Seng-Pan, RP Martins
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
552015
Design and experimental verification of a power effective flash-SAR subranging ADC
UF Chio, HG Wei, Y Zhu, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (8), 607-611, 2010
522010
Two-step channel selection for wireless receiver front-ends
PI Mak, U Seng-Pan, RP da Silva Martins
US Patent 7,529,322, 2009
522009
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC
SS Wong, UF Chio, Y Zhu, SW Sin, U Seng-Pan, RP Martins
IEEE journal of solid-state circuits 48 (8), 1783-1794, 2013
502013
Limit cycle oscillation reduction for digital low dropout regulators
M Huang, Y Lu, SW Sin, U Seng-Pan, RP Martins, WH Ki
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (9), 903-907, 2016
492016
20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors
Y Lu, J Jiang, WH Ki, CP Yue, SW Sin, U Seng-Pan, RP Martins
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
472015
A two-way interleaved 7-b 2.4-GS/s 1-then-2 b/cycle SAR ADC with background offset calibration
CH Chan, Y Zhu, WH Zhang, U Seng-Pan, RP Martins
IEEE Journal of Solid-State Circuits 53 (3), 850-860, 2018
442018
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