Erik Jan Marinissen

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Sandeep Kumar GoelAcademician/Director, TSMCVerified email at tsmc.com
Krishnendu ChakrabartyFulton Professor of Microelectronics, School of Electrical and Computer and Energy EngineeringVerified email at asu.edu
Said HamdiouiDelft University of TechnologyVerified email at tudelft.nl
Mottaqiallah TaouilDelft University of TechnologyVerified email at tudelft.nl
Mario KonijnenburgPrincipal Member of Technical StaffVerified email at imec.nl
Eric BeyneSenior Fellow, VP R&DVerified email at imec.be
Dimitrios VelenisimecVerified email at imec.be
Sergej DeutschIntel CorporationVerified email at intel.com
Siddharth RaoResearcher, IMEC, BelgiumVerified email at imec.be
Kees GoossensProfessor in Real-Time Embedded Systems, Eindhoven university of TechnologyVerified email at tue.nl
Lizhou WuDelf University of TechnologyVerified email at tudelft.nl
Vivek ChickermaneDistinguished Engineer, Cadence Design SystemsVerified email at cadence.com
Cheng-Wen Wu 吳誠文Department of Electrical Engineering, National Tsing Hua UniversityVerified email at ee.nthu.edu.tw
Ferenc FodorChercheur, EDF R&DVerified email at edf.fr
Gouri Sankar KarVP R&D, IMEC BelgiumVerified email at imec.be
Sujit DeyProfessor of Electrical and Computer Engineering, University of California, San DiegoVerified email at ucsd.edu
Harald VrankenOpen Universiteit & Radboud UniversiteitVerified email at ou.nl
Hailong JIAOPeking UniversityVerified email at pku.edu.cn
Hans-Joachim WunderlichProfessor Emeritus of Computer Science, University of StuttgartVerified email at informatik.uni-stuttgart.de
Jos HuiskenAlways looking for new challenges ;-)Verified email at jostinako.com

Erik Jan Marinissen

Scientific Director at imec

Verified email at imec.be - Homepage

Test and debug of integrated circuits


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Testing embedded-core based system chips Y Zorian, EJ Marinissen, S Dey Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998	818	1998
Test wrapper and test access mechanism co-optimization for system-on-chip V Iyengar, K Chakrabarty, EJ Marinissen Journal of Electronic Testing 18, 213-230, 2002	500	2002
A structured and scalable mechanism for test access to embedded reusable cores EJ Marinissen, R Arendsen, G Bos, H Dingemanse, M Lousberg, ... Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998	453	1998
A set of benchmarks for modular testing of SOCs EJ Marinissen, V Iyengar, K Chakrabarty Proceedings. International Test Conference, 519-528, 2002	404	2002
Testing 3D chips containing through-silicon vias EJ Marinissen, Y Zorian 2009 International Test Conference, 1-11, 2009	393	2009
Wrapper design for embedded core test EJ Marinissen, SK Goel, M Lousberg Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000	345	2000
Scan chain design for test time reduction in core-based ICs J Aerts, EJ Marinissen Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998	267	1998
On using rectangle packing for SOC wrapper/TAM co-optimization V Iyengar, K Chakrabarty, EJ Marinissen Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 253-258, 2002	231	2002
Effective and efficient test architecture design for SOCs SK Goel, EJ Marinissen Proceedings. International Test Conference, 529-538, 2002	230	2002
Towards a standard for embedded core test: An example EJ Marinissen, Y Zorian, R Kapur, T Taylor, L Whetsel International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999	215	1999
A structured and scalable test access architecture for TSV-based 3D stacked ICs EJ Marinissen, J Verbree, M Konijnenburg 2010 28th VLSI Test Symposium (VTS), 269-274, 2010	196	2010
On IEEE P1500’s standard for embedded core test EJ Marinissen, R Kapur, M Lousberg, T McLaurin, M Ricchetti, Y Zorian, ... SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 1-19, 2002	186	2002
Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip K Chakrabarty, EJ Marinissen IEEE Transactions on Computers 52 (12), 1619-1632, 2003	163	2003
Challenges in embedded memory design and test EJ Marinissen, B Prince, D Keltel-Schulz, Y Zorian Design, Automation and Test in Europe, 722-727, 2005	132	2005
SOC test architecture design for efficient utilization of test bandwidth SK Goel, EJ Marinissen ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003	128	2003
Application of deterministic logic BIST on industrial circuits G Kiefer, H Vranken, E Jan Marinissen, HJ Wunderlich Journal of Electronic Testing 17, 351-362, 2001	126	2001
Challenges and emerging solutions in testing TSV-based 2 1 over 2D-and 3D-stacked ICs EJ Marinissen 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012	125	2012
Testing TSV-based three-dimensional stacked ICs EJ Marinissen 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010	124	2010
Impact of 3D design choices on manufacturing cost D Velenis, M Stucchi, EJ Marinissen, B Swinnen, E Beyne 2009 IEEE International Conference on 3D System Integration, 1-5, 2009	124	2009
Efficient wrapper/TAM co-optimization for large SOCs V Iyengar, K Chakrabarty, EJ Marinissen Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002	117	2002

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