Alexis Farcy
Alexis Farcy
Verified email at st.com
Title
Cited by
Cited by
Year
Innovative materials, devices, and CMOS technologies for low-power mobile multimedia
T Skotnicki, C Fenouillet-Beranger, C Gallon, F Boeuf, S Monfray, F Payet, ...
IEEE transactions on electron devices 55 (1), 96-130, 2007
2432007
A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications
F Boeuf, S Crémer, N Vulliet, T Pinguet, A Mekis, G Masini, L Verslegers, ...
2013 IEEE International Electron Devices Meeting, 13.3. 1-13.3. 4, 2013
972013
High frequency characterization and modeling of high density TSV in 3D integrated circuits
C Bermond, L Cadix, A Farcy, T Lacrevaz, P Leduc, B Flechet
2009 IEEE Workshop on Signal Propagation on Interconnects, 1-4, 2009
832009
Recent progress in silicon photonics R&D and manufacturing on 300mm wafer platform
F Boeuf, S Cremer, E Temporiti, M Fere, M Shaw, N Vulliet, B Orlando, ...
Optical Fiber Communication Conference, W3A. 1, 2015
752015
Reliable 300 mm wafer level hybrid bonding for 3D stacked CMOS image sensors
S Lhostis, A Farcy, E Deloffre, F Lorut, S Mermoz, Y Henrion, L Berthier, ...
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 869-876, 2016
732016
Euroserver: Energy efficient node for european micro-servers
Y Durand, PM Carpenter, S Adami, A Bilas, D Dutoit, A Farcy, ...
2014 17th Euromicro Conference on Digital System Design, 206-213, 2014
672014
Investigation on TSV impact on 65nm CMOS devices and circuits
H Chaabouni, M Rousseau, P Leduc, A Farcy, R El Farhane, A Thuaire, ...
2010 International Electron Devices Meeting, 35.1. 1-35.1. 4, 2010
602010
Modelling of through silicon via RF performance and impact on signal transmission in 3D integrated circuits
L Cadix, A Farcy, C Bermond, C Fuchs, P Leduc, M Rousseau, M Assous, ...
2009 IEEE International Conference on 3D System Integration, 1-7, 2009
572009
Sidewall restoration of porous ultra low-k dielectrics for sub-45 nm technology nodes
H Chaabouni, LL Chapelon, M Aimadeddine, J Vitiello, A Farcy, R Delsol, ...
Microelectronic Engineering 84 (11), 2595-2599, 2007
522007
Advanced Cu interconnects using air gaps
LG Gosset, A Farcy, J De Pontcharra, P Lyan, R Daamen, G Verheijden, ...
Microelectronic engineering 82 (3-4), 321-332, 2005
442005
An evaluation of the CMOS technology roadmap from the point of view of variability, interconnects, and power dissipation
F Boeuf, M Sellier, A Farcy, T Skotnicki
IEEE Transactions on Electron Devices 55 (6), 1433-1440, 2008
422008
Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method
S Joblot, A Farcy, JF Carpentier, P Bar
US Patent 8,841,749, 2014
402014
RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking
L Cadix, C Bermond, C Fuchs, A Farcy, P Leduc, L DiCioccio, M Assous, ...
Microelectronic Engineering 87 (3), 491-495, 2010
402010
A cost-effective low power platform for the 45-nm technology node
E Josse, S Parihar, O Callen, P Ferreira, C Monget, A Farcy, M Zaleski, ...
2006 International Electron Devices Meeting, 1-4, 2006
382006
Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding …
A Farcy, P Coronel, P Ancey, J Torres
US Patent 6,846,690, 2005
382005
32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k= 2.3
K Hamioud, V Arnal, A Farcy, V Jousseaume, A Zenasni, B Icard, ...
Microelectronic engineering 87 (3), 316-320, 2010
332010
Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology
M Rousseau, O Rozeau, G Cibrario, G Le Carval, MA Jaud, P Leduc, ...
IMAPS Device Packaging Conference, Session WA1: wafer-level 3D integration …, 2008
332008
Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs
L Cadix, M Rousseau, C Fuchs, P Leduc, A Thuaire, R El Farhane, ...
2010 IEEE International Interconnect Technology Conference, 1-3, 2010
322010
Impact of patterning and ashing on electrical properties and reliability of interconnects in a porous SiOCH ultra low-k dielectric material
M Aimadeddine, V Arnal, A Farcy, C Guedj, T Chevolleau, N Posseme, ...
Microelectronic engineering 82 (3-4), 341-347, 2005
322005
An efficient algorithm for 3D interconnect capacitance extraction considering floating conductors
O Cueto, F Charlet, A Farcy
International Conference on Simulation of Semiconductor Processes and …, 2002
312002
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