Suman Sau
Cited by
Cited by
Challenges in QCD matter physics--The scientific programme of the Compressed Baryonic Matter experiment at FAIR
T Ablyazimov, A Abuhoza, RP Adak, M Adamczyk, K Agarwal, ...
The European Physical Journal A 53, 1-14, 2017
A new high throughput and area efficient SHA-3 implementation
MM Wong, J Haj-Yahya, S Sau, A Chattopadhyay
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
IoT based secure smart city architecture using blockchain
R Paul, P Baidya, S Sau, K Maity, S Maity, SB Mandal
2018 2nd international conference on data science and business analytics …, 2018
Design of an FPGA based intelligence traffic light controller with VHDL
S Nath, C Pal, S Sau, S Mukherjee, A Roy, A Guchhait, D Kandar
2012 International Conference on Radar, Communication and Computing (ICRCC …, 2012
Survey of secure processors
S Sau, J Haj-Yahya, MM Wong, KY Lam, A Chattopadhyay
2017 International Conference on Embedded Computer Systems: Architectures …, 2017
Blockchain based secure smart city architecture using low resource IoTs
R Paul, N Ghosh, S Sau, A Chakrabarti, P Mohapatra
Computer Networks 196, 108234, 2021
Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication
R Paul, S Saha, S Sau, A Chakrabarti
arXiv preprint arXiv:1205.2153, 2012
A novel method for soft error mitigation in FPGA using modified matrix code
S Mandal, R Paul, S Sau, A Chakrabarti, S Chattopadhyay
IEEE Embedded Systems Letters 8 (4), 65-68, 2016
The future of the Arecibo Observatory: The Next Generation Arecibo Telescope
DA Roshi, N Aponte, E Araya, H Arce, LA Baker, W Baan, TM Becker, ...
arXiv preprint arXiv:2103.01367, 2021
A modified support vector regression approach for failure analysis in beam-like structures
S Choudhury, DN Thatoi, K Maity, S Sau, MD Rao
Journal of Failure Analysis and Prevention 18 (4), 998-1009, 2018
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware
S Mandal, R Paul, S Sau, A Chakrabarti, S Chattopadhyay
Microprocessors and Microsystems 51, 313-330, 2017
Real time communication between multiple FPGA systems in multitasking environment using RTOS
R Paul, S Saha, S Sau, A Chakrabarti
2012 International Conference on Devices, Circuits and Systems (ICDCS), 130-134, 2012
Predicting crack in a beam-like structure through an over fitting verified regression model
S Choudhury, DN Thatoi, J Hota, S Sau, MD Rao
Multidiscipline Modeling in Materials and Structures 15 (6), 1190-1211, 2019
A novel AES-256 implementation on FPGA using co-processor based architecture
S Sau, R Paul, T Biswas, A Chakrabarti
Proceedings of the International Conference on Advances in Computing …, 2012
Novel architecture of modular exponent on reconfigurable system
R Paul, S Saha, C Pal, S Sau
2012 Students Conference on Engineering and Systems, 1-6, 2012
Design and implementation of real time secured rs232 link for multiple fpga communication
S Sau, C Pal, A Chakrabarti
Proceedings of the 2011 International Conference on Communication, Computing …, 2011
Hardware implementation of parallel FIR filter using modified distributed arithmetic
G Das, K Maity, S Sau
2018 2nd International Conference on Data Science and Business Analytics …, 2018
Internal monitoring of GBTx emulator using IPbus for CBM experiment
S Mandal, W Zabolotny, S Sau, A Chkrabarti, J Saini, S Chattopadhyay, ...
Photonics Applications in Astronomy, Communications, Industry, and High …, 2015
A brief experience on journey through hardware developments for image processing and its applications on Cryptography
S Saha, S Maity, S Sau
arXiv preprint arXiv:1212.6303, 2012
Architecture for real time continuous sorting on large width data volume for FPGA based applications
R Paul, S Sau, A Chakrabarti
arXiv preprint arXiv:1206.1567, 2012
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