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Soumya Eachempati
Soumya Eachempati
Pennsylvania State University
Adresse e-mail validée de intel.com
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MIRA: A multi-layered on-chip interconnect router architecture
D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das
2008 International Symposium on Computer Architecture, 251-261, 2008
2872008
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
R Das, S Eachempati, AK Mishra, V Narayanan, CR Das
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
2492009
A case for dynamic frequency tuning in on-chip networks
AK Mishra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, CR Das
2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture …, 2009
1442009
Assessing carbon nanotube bundle interconnect for future FPGA architectures
S Eachempati, A Nieuwoudt, A Gayasen, N Vijaykrishnan, Y Massoud
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
752007
RAFT: A router architecture with frequency tuning for on-chip networks
AK Mishra, A Yanamandra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, ...
Journal of Parallel and Distributed Computing 71 (5), 625-640, 2011
372011
Automated mapping for reconfigurable single-electron transistor arrays
YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan
2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 878-883, 2011
272011
Reconfigurable BDD based quantum circuits
S Eachempati, V Saripalli, N Vijaykrishnan, S Datta
2008 IEEE International Symposium on Nanoscale Architectures, 61-67, 2008
262008
A synthesis algorithm for reconfigurable single-electron transistor arrays
YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (1), 1-20, 2013
202013
Optimizing power and performance for reliable on-chip networks
A Yanamandra, S Eachempati, N Soundararajan, V Narayanan, MJ Irwin, ...
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 431-436, 2010
202010
Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines
R Manimegalai, ES Soumya, V Muralidharan, B Ravindran, V Kamakoti
VLSI Design, 2005. 18th International Conference on, 451-456, 2005
202005
Design and evaluation of hierarchical on-chip network topologies for next generation CMPs
R Das, S Eachempati, AK Mishra, N Vijaykrishnan, CR Das
HPCA-15 2, 2009
162009
Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect
S Eachempati, N Vijaykrishnan, A Nieuwoudt, Y Massoud
IET circuits, devices & systems 3 (2), 64-75, 2009
142009
Leveraging emerging technology through architectural exploration for the routing fabric of future FPGAs
S Eachempati, A Gayasen, N Vijaykrishnan, MJ Irwin
Nanoelectronic Circuit Design, 189-213, 2011
42011
Impact of process variations on carbon nanotube bundle interconnect for future FPGA architectures
S Eachempati, N Vijaykrishnan, A Nieuwoudt, Y Massoud
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 516-517, 2007
42007
Reetuparna Das, Asit K Mishra, Yuan Xie, Narayanan Vijaykrishnan, and Chita R Das. 2008. MIRA: a multi-layered on-chip interconnect router architecture
D Park, S Eachempati
ACM SIGARCH Computer Architecture News 36, 251-261, 0
4
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network
Y Xie, S Eachempati, A Yanamandra, V Narayanan, MJ Irwin
2009 IEEE/ACM International Symposium on Nanoscale Architectures, 51-56, 2009
22009
HeTERO: Hybrid Topology Exploration for RF-Based On-Chip Networks
S Eachempati, R Das, V Narayanan, Y Xie, S Datta, CR Das
Communication Architectures for Systems-on-Chip, 231-278, 2018
2018
HeTERO: Hybrid Topology Exploration for RF-Based On-Chip Networks
S Eachempati, R Das, V Narayanan, Y Xie, S Datta, CR Das
Communication Architectures for Systems-on-Chip, 231-278, 2018
2018
Three-dimensional On-chip Interconnect Architectures
S Eachempati, D Park, R Das, AK Mishra, V Narayanan, Y Xie, C Das
Designing Network On-Chip Architectures in the Nanoscale Era, 391-420, 2010
2010
Non-silicon logic elements on silicon for extreme voltage scaling
S Datta, A Ali, S Mookerjea, V Saripalli, L Liu, S Eachempati, T Mayer, ...
2010 Silicon Nanoelectronics Workshop, 1-2, 2010
2010
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