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Dr. Casey Smith
Dr. Casey Smith
Shared Research Operations Manager, Cleanroom Director, Texas State University
Adresse e-mail validée de txstate.edu - Page d'accueil
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Si tunnel transistors with a novel silicided source and 46mV/dec swing
K Jeon, WY Loh, P Patel, CY Kang, J Oh, A Bowonder, C Park, CS Park, ...
2010 Symposium on VLSI Technology, 121-122, 2010
2232010
Silicon nanotube field effect transistor with core–shell gate stacks for enhanced high-performance operation and area scaling benefits
HM Fahad, CE Smith, JP Rojas, MM Hussain
Nano letters 11 (10), 4393-4399, 2011
1662011
Imaging local electronic corrugations and doped regions in graphene
BJ Schultz, CJ Patridge, V Lee, C Jaye, PS Lysaght, C Smith, J Barnett, ...
Nature communications 2 (1), 372, 2011
1202011
A family of memristor‐based reactance‐less oscillators
MA Zidan, H Omran, C Smith, A Syed, AG Radwan, KN Salama
International Journal of Circuit Theory and Applications 42 (11), 1103-1122, 2014
932014
Substrate hybridization and rippling of graphene evidenced by near-edge X-ray absorption fine structure spectroscopy
V Lee, C Park, C Jaye, DA Fischer, Q Yu, W Wu, Z Liu, J Bao, SS Pei, ...
The journal of physical chemistry letters 1 (8), 1247-1253, 2010
782010
Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme
HR Harris, P Kalra, P Majhi, M Hussain, D Kelly, J Oh, D He, C Smith, ...
2007 IEEE Symposium on VLSI Technology, 154-155, 2007
702007
Flexible and transparent silicon‐on‐polymer based sub‐20 nm non‐planar 3D FinFET for brain‐architecture inspired computation
GAT Sevilla, JP Rojas, HM Fahad, AM Hussain, R Ghanem, CE Smith, ...
Advanced Materials 26 (18), 2794-2799, 2014
692014
Advanced technology for source drain resistance reduction in nanoscale FinFETs
CE Smith
University of North Texas, 2008
512008
Cylindrical-shaped nanotube field effect transistor
MM Hussain, HM Fahad, CE Smith, JP Rojas
US Patent 9,224,813, 2015
502015
Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow
RJW Hill, C Park, J Barnett, J Price, J Huang, N Goel, WY Loh, J Oh, ...
2010 International Electron Devices Meeting, 6.2. 1-6.2. 4, 2010
492010
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS
HF Dadgour, MM Hussain, C Smith, K Banerjee
Proceedings of the 47th Design Automation Conference, 893-896, 2010
492010
Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-/Metal Gates CMOS FinFETs for Multi- Engineering
MM Hussain, CE Smith, HR Harris, CD Young, HH Tseng, R Jammy
IEEE transactions on electron devices 57 (3), 626-631, 2010
482010
SILICON FINFETS AS DETECTORS OF TERAHERTZ AND SUB-TERAHERTZ RADIATION
W Stillman, C Donais, S Rumyantsev, M Shur, D Veksler, C Hobbs, ...
International Journal of High Speed Electronics and Systems 20 (01), 27-42, 2011
472011
Simplistic graphene transfer process and its impact on contact resistance
MT Ghoneim, CE Smith, MM Hussain
Applied Physics Letters 102 (18), 2013
462013
Contact resistance reduction to FinFET source/drain using novel dielectric dipole Schottky barrier height modulation method
BE Coss, C Smith, WY Loh, P Majhi, RM Wallace, J Kim, R Jammy
IEEE electron device letters 32 (7), 862-864, 2011
362011
Critical discussion on (100) and (110) orientation dependent transport: nMOS planar and FinFET
CD Young, MO Baykan, A Agrawal, H Madan, K Akarvardar, C Hobbs, ...
2011 Symposium on VLSI Technology-Digest of Technical Papers, 18-19, 2011
352011
Comparison of uniaxial wafer bending and contact-etch-stop-liner stress induced performance enhancement on double-gate FinFETs
S Suthram, MM Hussain, HR Harris, C Smith, HH Tseng, R Jammy, ...
IEEE electron device letters 29 (5), 480-482, 2008
342008
(1 1 0) and (1 0 0) Sidewall-oriented FinFETs: A performance and reliability investigation
CD Young, K Akarvardar, MO Baykan, K Matthews, I Ok, T Ngai, KW Ang, ...
Solid-state electronics 78, 2-10, 2012
302012
Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node
CE Smith, H Adhikari, SH Lee, B Coss, S Parthasarathy, C Young, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
272009
Measurement of high-k and metal film thickness on FinFET sidewalls using scatterometry
TG Dziura, B Bunday, C Smith, MM Hussain, R Harris, X Zhang, JM Price
Metrology, Inspection, and Process Control for Microlithography XXII 6922 …, 2008
252008
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