| Wafer map defect pattern classification and image retrieval using convolutional neural network T Nakazawa, DV Kulkarni IEEE Transactions on Semiconductor Manufacturing 31 (2), 309-314, 2018 | 352 | 2018 |
| Anomaly detection and segmentation for wafer defect patterns using deep convolutional encoder–decoder neural network architectures in semiconductor manufacturing T Nakazawa, DV Kulkarni IEEE Transactions on Semiconductor Manufacturing 32 (2), 250-256, 2019 | 138 | 2019 |
| Localized high density substrate routing R Starkston, D Mallik, JS Guzek, CP Chiu, D Kulkarni, RV Mahajan US Patent 9,136,236, 2015 | 97* | 2015 |
| Localized high density substrate routing R Starkston, D Mallik, JS Guzek, CP Chiu, D Kulkarni, RV Mahajan US Patent 9,269,701, 2016 | 48 | 2016 |
| Bumpless build-up layer package including an integrated heat spreader WH Teh, D Kulkarni, CP Chiu, T Harirchian, JS Guzek US Patent 8,912,670, 2014 | 45 | 2014 |
| A Newton–Schur alternative to the consistent tangent approach in computational plasticity DV Kulkarni, DA Tortorelli, M Wallin Computer methods in applied mechanics and engineering 196 (7), 1169-1177, 2007 | 44 | 2007 |
| Bumpless build-up layer package including an integrated heat spreader WH Teh, D Kulkarni, CP Chiu, T Harirchian, JS Guzek US Patent 9,153,552, 2015 | 30 | 2015 |
| Bumpless build-up layer package including an integrated heat spreader WH Teh, D Kulkarni, CP Chiu, T Harirchian, JS Guzek US Patent 9,520,376, 2016 | 11 | 2016 |
| Logic die and other components embedded in build-up layers DV Kulkarni, RK Mortensen, JS Guzek US Patent 9,496,211, 2016 | 11 | 2016 |
| Techniques for die tiling S Pietambaram, G Duan, D Kulkarni US Patent App. 15/949,141, 2019 | 7 | 2019 |
| Discontinuous Galerkin framework for adaptive solution of parabolic problems DV Kulkarni, DV Rovas, DA Tortorelli International journal for numerical methods in engineering 70 (1), 1-24, 2007 | 7 | 2007 |
| A domain decomposition based two-level Newton scheme for nonlinear problems DV Kulkarni, DA Tortorelli Domain decomposition methods in science and engineering, 615-622, 2005 | 7 | 2005 |
| IC substrate package yield prediction model and layer level risk assessment by design analysis T Nakazawa, DV Kulkarni, OA Martin IEEE Transactions on Semiconductor Manufacturing 29 (3), 257-262, 2016 | 6 | 2016 |
| BBUL MATERIAL INTEGRATION IN-PLANE WITH EMBEDDED DIE FOR WARPAGE CONTROL WH Teh, K DV US Patent 9,601,421, 2014 | 6 | 2014 |
| Microelectronic structures including bridges B Nie, KK Darmawikarta, SV Pietambaram, C Haobo, G Duan, JM Gamba, ... US Patent App. 16/902,959, 2021 | 5 | 2021 |
| A dynamic model for predicting the motion of solder droplets during assembly D Kulkarni, G Subbarayan ITHERM 2000. The Seventh Intersociety Conference on Thermal and …, 2000 | 4 | 2000 |
| A discontinuous Galerkin formulation for solution of parabolic equations on nonconforming meshes DV Kulkarni, DV Rovas, DA Tortorelli Domain decomposition methods in science and engineering XVI, 651-658, 2007 | 3 | 2007 |
| Logic die and other components embedded in build-up layers DV Kulkarni, RK Mortensen, JS Guzek US Patent 10,453,799, 2019 | 2 | 2019 |
| Techniques for die tiling S Pietambaram, G Duan, D Kulkarni US Patent App. 18/216,275, 2023 | 1 | 2023 |
| Localized high density substrate routing R Starkston, D Mallik, JS Guzek, CP Chiu, D Kulkarni, RV Mahajan US Patent 11,515,248, 2022 | 1 | 2022 |
Weng Hong TehAdresse e-mail validée de alum.mit.edu
