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Remi Coquand
Remi Coquand
Advanced devices Engineer, PhD
Verified email at cea.fr
Title
Cited by
Cited by
Year
Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm
S Barraud, M Berthome, R Coquand, M Cassé, T Ernst, MP Samson, ...
IEEE Electron Device Letters 33 (9), 1225-1227, 2012
2522012
Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm
S Barraud, R Coquand, M Casse, M Koyama, JM Hartmann, ...
IEEE Electron Device Letters 33 (11), 1526-1528, 2012
1622012
Vertically stacked-nanowires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
S Barraud, V Lapras, MP Samson, L Gaben, L Grenouillet, ...
2016 IEEE International Electron Devices Meeting (IEDM), 17.6. 1-17.6. 4, 2016
1132016
Strain-induced performance enhancement of trigate and omega-gate nanowire FETs scaled down to 10-nm width
R Coquand, M Casse, S Barraud, D Cooper, V Maffini-Alvaro, ...
IEEE Transactions on Electron Devices 60 (2), 727-732, 2012
972012
Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width
R Coquand, S Barraud, M Cassé, P Leroux, C Vizioz, C Comboroure, ...
Solid-State Electronics 88, 32-36, 2013
832013
Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width
R Coquand, S Barraud, M Cassé, P Leroux, C Vizioz, C Comboroure, ...
Solid-State Electronics 88, 32-36, 2013
832013
Method for making a semiconductor device with self-aligned inner spacers
S Reboh, E Augendre, R Coquand
US Patent 10,217,842, 2019
462019
Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications
G Piccolboni, G Molas, JM Portal, R Coquand, M Bocquet, D Garbin, ...
2015 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2015
412015
Scaling of Ω-gate SOI nanowire N-and P-FET down to 10nm gate length: Size-and orientation-dependent strain effects
S Barraud, R Coquand, V Maffini-Alvaro, MP Samson, JM Hartmann, ...
2013 Symposium on VLSI Technology, T230-T231, 2013
402013
Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology
S Reboh, R Coquand, S Barraud, N Loubet, N Bernier, G Audoit, ...
Applied Physics Letters 112 (5), 2018
352018
Scaling of trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to single electron transistor
V Deshpande, S Barraud, X Jehl, R Wacquez, M Vinet, R Coquand, ...
Solid-state electronics 84, 179-184, 2013
312013
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs
M Koyama, M Cassé, R Coquand, S Barraud, C Vizioz, C Comboroure, ...
Solid-state electronics 84, 46-52, 2013
232013
Enhanced performance of P-FET omega-gate SoI nanowire with recessed-SiGe source-drain down to 13-nm gate length
S Barraud, R Coquand, JM Hartmann, V Maffini-Alvaro, MP Samson, ...
IEEE electron device letters 34 (9), 1103-1105, 2013
222013
Density Gradient calibration for 2D quantum confinement: Tri-Gate SOI transistor application
N Pons, F Triozon, MA Jaud, R Coquand, S Martinie, O Rozeau, ...
2013 international conference on simulation of semiconductor processes and …, 2013
172013
Study of piezoresistive properties of advanced CMOS transistors: thin film SOI, SiGe/SOI, unstrained and strained tri-gate nanowires
M Cassé, S Barraud, C Le Royer, M Koyama, R Coquand, D Blachier, ...
2012 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2012
172012
Imaging, modeling and engineering of strain in gate-all-around nanosheet transitors
S Reboh, R Coquand, N Loubet, N Bernier, E Augendre, R Chao, J Li, ...
2019 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2019
162019
Method for making a semiconductor device with a compressive stressed channel
S Reboh, E Augendre, R Coquand, N Loubet
US Patent 10,431,683, 2019
162019
300 K operating full-CMOS integrated single electron transistor (SET)-FET circuits
V Deshpande, R Wacquez, M Vinet, X Jehl, S Barraud, R Coquand, ...
2012 International Electron Devices Meeting, 8.7. 1-8.7. 4, 2012
162012
Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies
S Barraud, B Previtali, V Lapras, R Coquand, C Vizioz, JM Hartmann, ...
Semiconductor Science and Technology 34 (7), 074001, 2019
152019
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities
V Deshpande, S Barraud, X Jehl, R Wacquez, M Vinet, R Coquand, ...
2012 Proceedings of the European Solid-State Device Research Conference …, 2012
152012
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