| Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET Y Choi, K Lee, KY Kim, S Kim, J Lee, R Lee, HM Kim, YS Song, S Kim, ... Solid-State Electronics 164, 107686, 2020 | 49 | 2020 |
| Wakeup-free and endurance-robust ferroelectric field-effect transistor memory using high pressure annealing MC Nguyen, S Kim, K Lee, JY Yim, R Choi, D Kwon IEEE Electron Device Letters 42 (9), 1295-1298, 2021 | 42 | 2021 |
| Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs S Kim, M Kim, D Ryu, K Lee, S Kim, J Lee, R Lee, S Kim, JH Lee, BG Park IEEE Transactions on Electron Devices 67 (6), 2648-2652, 2020 | 38 | 2020 |
| Effects of high-pressure annealing on the low-frequency noise characteristics in ferroelectric FET W Shin, JH Bae, S Kim, K Lee, D Kwon, BG Park, D Kwon, JH Lee IEEE Electron Device Letters 43 (1), 13-16, 2021 | 35 | 2021 |
| Ferroelectric-gate field-effect transistor memory with recessed channel K Lee, JH Bae, S Kim, JH Lee, BG Park, D Kwon IEEE Electron Device Letters 41 (8), 1201-1204, 2020 | 27 | 2020 |
| Design and optimization of triple-k spacer structure in two-stack nanosheet FET from OFF-state leakage perspective D Ryu, M Kim, S Kim, Y Choi, J Yu, JH Lee, BG Park IEEE Transactions on Electron Devices 67 (3), 1317-1322, 2020 | 27 | 2020 |
| Incremental drain-voltage-ramping training method for ferroelectric field-effect transistor synaptic devices MC Nguyen, K Lee, S Kim, S Youn, Y Hwang, H Kim, R Choi, D Kwon IEEE Electron Device Letters 43 (1), 17-20, 2021 | 18 | 2021 |
| Effects of process-induced defects on polarization switching in ferroelectric tunneling junction memory K Lee, S Kim, JH Lee, BG Park, D Kwon IEEE Electron Device Letters 42 (3), 323-326, 2021 | 18 | 2021 |
| Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond S Kim, K Lee, S Kim, M Kim, JH Lee, S Kim, BG Park IEEE Transactions on Electron Devices 69 (4), 2088-2093, 2022 | 16 | 2022 |
| Multiplexed silicon nanowire tunnel FET-based biosensors with optimized multi-sensing currents S Kim, R Lee, D Kwon, TH Kim, TJ Park, SJ Choi, HS Mo, DH Kim, ... IEEE Sensors Journal 21 (7), 8839-8846, 2021 | 16 | 2021 |
| Vertically stacked gate-all-around structured tunneling-based ternary-CMOS S Kim, K Lee, JH Lee, D Kwon, BG Park IEEE Transactions on Electron Devices 67 (9), 3889-3893, 2020 | 16 | 2020 |
| Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique J Lee, R Lee, S Kim, K Lee, HM Kim, S Kim, M Kim, S Kim, JH Lee, ... Solid-State Electronics 164, 107701, 2020 | 16 | 2020 |
| Nanowire size dependence on sensitivity of silicon nanowire field-effect transistor-based pH sensor R Lee, DW Kwon, S Kim, S Kim, HS Mo, DH Kim, BG Park Japanese Journal of Applied Physics 56 (12), 124001, 2017 | 16 | 2017 |
| Drift-free pH detection with silicon nanowire field-effect transistors D Kwon, JH Lee, S Kim, R Lee, H Mo, J Park, DH Kim, BG Park IEEE Electron Device Letters 37 (5), 652-655, 2016 | 16 | 2016 |
| Demonstration of tunneling field-effect transistor ternary inverter HW Kim, S Kim, K Lee, J Lee, BG Park, D Kwon IEEE Transactions on Electron Devices 67 (10), 4541-4544, 2020 | 15 | 2020 |
| Investigation of feasibility of tunneling field effect transistor (TFET) as highly sensitive and multi-sensing biosensors R Lee, DW Kwon, S Kim, DH Kim, BG Park JSTS: Journal of Semiconductor Technology and Science 17 (1), 141-146, 2017 | 14 | 2017 |
| Investigation of drift effect on silicon nanowire field effect transistor based pH sensor S Kim, DW Kwon, R Lee, DH Kim, BG Park Japanese Journal of Applied Physics 55 (6S1), 06GG01, 2016 | 14 | 2016 |
| Analysis on reverse drain-induced barrier lowering and negative differential resistance of ferroelectric-gate field-effect transistor memory K Lee, S Kim, JH Lee, D Kwon, BG Park IEEE Electron Device Letters 41 (8), 1197-1200, 2020 | 13 | 2020 |
| A novel fabrication method for co-integrating ISFET with damage-free sensing oxide and threshold voltage-tunable CMOS read-out circuits DW Kwon, R Lee, S Kim, HS Mo, DH Kim, BG Park Sensors and Actuators B: Chemical 260, 627-634, 2018 | 13 | 2018 |
| Negative capacitance effect on MOS structure: Influence of electric field variation K Lee, J Lee, S Kim, R Lee, S Kim, M Kim, JH Lee, S Kim, BG Park IEEE Transactions on Nanotechnology 19, 168-171, 2020 | 12 | 2020 |
Byung Gook ParkProfessor of Electrical Engineering, Seoul National UniversityAdresse e-mail validée de snu.ac.kr
