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Andreas Sembrant
Andreas Sembrant
Nvidia
Adresse e-mail validée de sembrant.com
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Efficient software-based online phase classification
A Sembrant, D Eklov, E Hagersten
2011 IEEE International Symposium on Workload Characterization (IISWC), 104-115, 2011
592011
Modeling performance variation due to cache sharing
A Sandberg, A Sembrant, E Hagersten, D Black-Schaffer
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
542013
Tlc: A tag-less cache for reducing dynamic first level cache energy
A Sembrant, E Hagersten, D Black-Shaffer
Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013
462013
Power-sleuth: A tool for investigating your program's power behavior
V Spiliopoulos, A Sembrant, S Kaxiras
2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation …, 2012
462012
Phase guided profiling for fast cache modeling
A Sembrant, D Black-Schaffer, E Hagersten
Proceedings of the Tenth International Symposium on Code Generation and …, 2012
352012
Phase behavior in serial and parallel applications
A Sembrant, D Black-Schaffer, E Hagersten
2012 IEEE International Symposium on Workload Characterization (IISWC), 47-58, 2012
342012
Long term parking (ltp) criticality-aware resource allocation in ooo processors
A Sembrant, T Carlson, E Hagersten, D Black-Shaffer, A Perais, A Seznec, ...
Proceedings of the 48th International Symposium on Microarchitecture, 334-346, 2015
252015
The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup
A Sembrant, E Hagersten, D Black-Schaffer
Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on …, 2014
232014
Cost-effective speculative scheduling in high performance processors
A Perais, A Seznec, P Michaud, A Sembrant, E Hagersten
ACM SIGARCH Computer Architecture News 43 (3S), 247-259, 2015
172015
Systems and methods for implementing a tag-less shared cache and a larger backing cache
E Hagersten, A Sembrant, D Black-schaffer, S Kaxiras
US Patent 10,402,331, 2019
162019
Management of shared pipeline resource usage based on level information
E Hagersten, A Sembrant, D Black-schaffer, S Kaxiras
US Patent 10,409,725, 2019
152019
Systems and methods for reducing first level cache energy by eliminating cache address tags
E Hagersten, A Sembrant, D Black-schaffer, S Kaxiras
US Patent 10,671,543, 2020
122020
A graphics tracing framework for exploring CPU+ GPU memory systems
A Sembrant, TE Carlson, E Hagersten, D Black-Schaffer
2017 IEEE International Symposium on Workload Characterization (IISWC), 54-65, 2017
102017
A split cache hierarchy for enabling data-oriented optimizations
A Sembrant, E Hagersten, D Black-Schaffer
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
102017
Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement
A Sembrant, E Hagersten, D Black-Schaffer
2016 IEEE 34th International Conference on Computer Design (ICCD), 117-124, 2016
72016
Placement policy for memory hierarchies
E Hagersten, A Sembrant, D Black-schaffer
US Patent 10,019,368, 2018
62018
Behind the scenes: Memory analysis of graphical workloads on tile-based GPUs
G Ceballos, A Sembrant, TE Carlson, D Black-Schaffer
2018 IEEE International Symposium on Performance Analysis of Systems and …, 2018
52018
Adaptive cache warming for faster simulations
G Borgström, A Sembrant, D Black-Schaffer
Proceedings of the 9th Workshop on Rapid Simulation and Performance …, 2017
52017
Systems and methods for efficient cacheline handling based on predictions
EE Hagersten, AK Sembrant, D Black-schaffer
US Patent 11,138,121, 2021
32021
Tracking alternative cacheline placement locations in a cache hierarchy
E Hagersten, A Sembrant, D Black-schaffer
US Patent 10,031,849, 2018
32018
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