Zheng Wang
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Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning
Z Wang, Y Chen, A Patil, X Zhang, CH Chang, A Basu
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
Fast reliability exploration for embedded processors via high-level fault injection
Z Wang, C Chen, A Chattopadhyay
International Symposium on Quality Electronic Design (ISQED), 265-272, 2013
Processor design with asymmetric reliability
Z Wang, G Paul, A Chattopadhyay
2014 IEEE Computer Society Annual Symposium on VLSI, 565-570, 2014
System-level reliability exploration framework for heterogeneous MPSoC
Z Wang, C Chen, P Sharma, A Chattopadhyay
Proceedings of the 24th edition of the great lakes symposium on VLSI, 9-14, 2014
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design
Z Wang, K Singh, C Chen, A Chattopadhyay
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 547-552, 2013
ASIC synthesis using architecture description language
Z Wang, X Wang, A Chattopadhyay, ZE Rakosi
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 1-4, 2012
A 2.86-TOPS/W Current Mirror Cross-Bar Based Machine-Learning and Physical Unclonable Function Engine for Internet-of-Things Applications
Y Chen, Z Wang, A Patil, A Basu
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019
Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance
JHF Constantin, Z Wang, G Karakonstantis, A Chattopadhyay, AP Burg
Design Automation Conference (DAC) 2016, 2016
Architectural Reliability Estimation using Design Diversity
Z Wang, Y Liu, A Chattopadhyay
International Symposium on Quality Electronic Design (ISQED), 2015, 2015
Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor
Z Wang, S Kanwal, L Wang, A Chattopadhyay
KMUTNB: International Journal of Applied Science and Technology., 2017
Current Mirror Array: a Novel Lightweight Strong PUF Topology with Enhanced Reliability
Z Wang, Y Chen, A Patil, CH Chang, A Basu
IEEE International Symposium on Circuits & Systems (ISCAS), 2017
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control
S Bian, M Shintani, Z Wang, M Hiromoto, A Chattopadhyay, T Sato
25th IEEE Asian Test Symposium (ATS), 2016
Power Modeling and Estimation during ADL-driven Embedded Processor Design
Z Wang, L Wang, H Xie, A Chattopadhyay
2013 4th Annual International Conference on Energy Aware Computing Systems …, 2013
Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting
M Marcu, O Boncalo, M Ghenea, A Amaricai, J Weinstock, R Leupers, ...
GI/ITG International Conference on Architecture of Computing Systems (ARCS), 2016
Direct FPGA-based power profiling for a RISC processor
C Cernazanu-Glavan, M Marcu, A Amaricai, S Fedeac, M Ghenea, ...
2015 IEEE International Instrumentation and Measurement Technology …, 2015
Opportunistic redundancy for improving reliability of embedded processors
Z Wang, R Li, A Chattopadhyay
Design and Test Symposium (IDT), 2013 8th International, 1-6, 2013
Low-cost vector map assisted navigation strategy for autonomous vehicle
W Li, X Meng, Z Wang, W Fang, J Zou, H Li, T Sun, J Liang
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018
A CGRA based Neural Network Inference Engine for Deep Reinforcement Learning
M Liang, M Chen, Z Wang, J Sun
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018
A Low Overhead Error Confinement Method based on Application Statistical Characteristics
Z Wang, G Karakonstantis, A Chattopadhyay
Design, Automation, and Test in Europe (DATE) 2016 - Best IP candidate, 2016
Accelerator design for convolutional neural network with vertical data streaming
S Li, N Ouyang, Z Wang
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018
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