AES on FPGA from the fastest to the smallest T Good, M Benaissa
Cryptographic Hardware and Embedded Systems–CHES 2005: 7th International …, 2005
319 2005 GF (2/sup m/) multiplication and division over the dual basis STJ Fenn, M Benaissa, D Taylor
IEEE Transactions on computers 45 (3), 319-327, 1996
222 1996 Fast elliptic curve cryptography on FPGA WN Chelton, M Benaissa
IEEE transactions on very large scale integration (VLSI) systems 16 (2), 198-205, 2008
212 2008 Hardware results for selected stream cipher candidates T Good, M Benaissa
State of the art of stream ciphers 7, 191-204, 2007
164 2007 Microcalorimetric and Fourier transform infrared spectroscopic studies of methanol adsorption on Al2O3 PF Rossi, V Lorenzelli, M BENAISSA, J Travert, JC Lavalley
Journal of physical chemistry (1952) 89 (25), 5433-5439, 1985
142 1985 Very small FPGA application-specific instruction processor for AES T Good, M Benaissa
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (7), 1477-1486, 2006
132 2006 High-Speed and Low-Latency ECC Processor Implementation Over GF( ZUA Khan, M Benaissa
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 165-176, 2016
95 2016 Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero RA Patel, M Benaissa, S Boussakta
Computers, IEEE Transactions on 56 (11), 1484 - 1492, 2007
90 2007 Throughput/area-efficient ECC processor using Montgomery point multiplication on FPGA M Benaissa
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (11), 1078-1082, 2015
86 2015 On-line error detection for bit-serial multipliers in GF (2m) S Fenn, M Gossel, M Benaissa, D Taylor
Journal of Electronic Testing 13, 29-40, 1998
84 1998 Bit-serial multiplication in GF (2m) using irreducible all-one polynomials STJ Fenn, MG Parker, M Benaissa, D Taylor
IEE Proceedings-Computers and Digital Techniques 144 (6), 391-393, 1997
78 1997 692-nW Advanced Encryption Standard (AES) on a 0.13- T Good, M Benaissa
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (12 …, 2009
74 2009 Hardware performance of eStream phase-III stream cipher candidates T Good, M Benaissa
Proc. of Workshop on the State of the Art of Stream Ciphers (SACS’08), 2008
73 2008 Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment) T Good, M Benaissa
IET Information Security 1 (1), 1-10, 2007
71 2007 Low area memory-free FPGA implementation of the AES algorithm J Chu, M Benaissa
22nd International Conference on Field Programmable Logic and Applications …, 2012
58 2012 Dual basis systolic multipliers for GF (2m) STJ Fenn, M Benaissa, D Taylor
IEE Proceedings-Computers and Digital Techniques 144 (1), 43-46, 1997
57 1997 Novel power-delay-area-efficient approach to generic modular addition RA Patel, M Benaissa, N Powell, S Boussakta
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (6), 1279-1292, 2007
54 2007 Robust eye blink detection based on eye landmarks and Savitzky–Golay filtering S Al-gawwam, M Benaissa
Information 9 (4), 93, 2018
52 2018 Simple and robust audio-based detection of biomarkers for Alzheimer’s disease S Al-Hameed, M Benaissa, H Christensen
7th Workshop on Speech and Language Processing for Assistive Technologies …, 2016
51 2016 ASIC hardware performance T Good, M Benaissa
New Stream Cipher Designs: The eSTREAM Finalists, 267-293, 2008
49 2008 
David TaylorUniversity of HuddersfieldAdresse e-mail validée de hud.ac.uk
