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Viorel Balan
Viorel Balan
CEA Leti
Verified email at cea.fr
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Cited by
Year
Vertically stacked-nanowires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
S Barraud, V Lapras, MP Samson, L Gaben, L Grenouillet, ...
2016 IEEE International Electron Devices Meeting (IEDM), 17.6. 1-17.6. 4, 2016
1132016
Reliable 300 mm wafer level hybrid bonding for 3D stacked CMOS image sensors
S Lhostis, A Farcy, E Deloffre, F Lorut, S Mermoz, Y Henrion, L Berthier, ...
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 869-876, 2016
1002016
3D Sequential Integration: Application-driven technological achievements and guidelines
P Batude, L Brunet, C Fenouillet-Beranger, F Andrieu, JP Colinge, ...
2017 IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2017
902017
Chalcogenide thin films deposited by radio-frequency sputtering
V Balan, C Vigreux, A Pradel
Journal of Optoelectronics and Advanced materials 6, 875-882, 2004
722004
Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness
J Jourdon, S Lhostis, S Moreau, J Chossat, M Arnoux, C Sart, Y Henrion, ...
2018 IEEE International Electron Devices Meeting (IEDM), 7.3. 1-7.3. 4, 2018
642018
Breakthroughs in 3D sequential technology
L Brunet, C Fenouillet-Beranger, P Batude, S Beaurepaire, F Ponthenier, ...
2018 IEEE International Electron Devices Meeting (IEDM), 7.2. 1-7.2. 4, 2018
572018
Investigation of the physical mechanisms governing data-retention in down to 10nm nano-trench Al2O3/CuTeGe conductive bridge RAM (CBRAM)
J Guy, G Molas, E Vianello, F Longnos, S Blanc, C Carabasse, M Bernard, ...
2013 IEEE International Electron Devices Meeting, 30.2. 1-30.2. 4, 2013
492013
1μm Pitch direct hybrid bonding with< 300nm wafer-to-wafer overlay accuracy
A Jouve, V Balan, N Bresson, C Euvrard-Colnat, F Fournel, Y Exbrayat, ...
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2017
452017
Chalcogenide glass-based rib ARROW waveguide
V Balan, C Vigreux, A Pradel, A Llobera, C Dominguez, MI Alonso, ...
Journal of non-crystalline solids 326, 455-459, 2003
402003
Tunability of parasitic channel in gate-all-around stacked nanosheets
S Barraud, B Previtali, V Lapras, C Vizioz, JM Hartmann, S Martinie, ...
2018 IEEE international Electron devices meeting (IEDM), 21.3. 1-21.3. 4, 2018
322018
Phase separation and ionic conductivity: an electric force microscopy investigation of silver chalcogenide glasses
V Balan, A Piarristeguy, M Ramonda, A Pradel, M Ribes
J. Optoelectron. Adv. Mater 8, 2112-2116, 2006
302006
Experimental and theoretical understanding of forming, SET and RESET operations in conductive bridge RAM (CBRAM) for memory stack optimization
J Guy, G Molas, P Blaise, C Carabasse, M Bernard, A Roule, G Le Carval, ...
2014 IEEE International Electron Devices Meeting, 6.5. 1-6.5. 4, 2014
282014
< 200 nm Wafer-to-wafer overlay accuracy in wafer level Cu/SiO2 hybrid bonding for BSI CIS
B Rebhan, M Bernauer, T Wagenleitner, M Heilig, F Kurz, S Lhostis, ...
2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 1-4, 2015
252015
Waveguides based upon chalcogenide glasses
V Balan, C Vigreux, A Pradel, M Ribes
Journal of Optoelectronics and Advanced Materials, 2001
222001
Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability
L Arnaud, S Moreau, A Jouve, I Jani, D Lattard, F Fournel, C Euvrard, ...
2018 IEEE International Reliability Physics Symposium (IRPS), 4D. 4-1-4D. 4-7, 2018
172018
Mass transport-induced failure of hybrid bonding-based integration for advanced image sensor applications
S Moreau, D Bouchu, V Balan, AL Le Berrigo, A Jouve, Y Henrion, ...
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1940-1945, 2016
172016
Method of planarizing recesses filled with copper
M Rivoire, V Balan
US Patent 9,620,385, 2017
152017
Guidelines for intermediate back end of line (BEOL) for 3D sequential integration
C Fenouillet-Beranger, S Beaurepaire, F Deprat, AA de Sousa, L Brunet, ...
2017 47th European Solid-State Device Research Conference (ESSDERC), 252-255, 2017
122017
Evaluation of stacked nanowires transistors for CMOS: Performance and technology opportunities
L Gaben, S Barraud, MP Samson, MA Jaud, S Martinie, O Rozeau, ...
ECS Transactions 72 (4), 43, 2016
122016
CMP process optimization for bonding applications
V Balan, A Seignard, D Scevola, JF Lugand, L Di Cioccio, M Rivoire
ICPT 2012-International Conference on Planarization/CMP Technology, 1-7, 2012
112012
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