Deleep R. Nair
Deleep R. Nair
Associate Professor, Department of Electrical Engg, IIT Madras
Adresse e-mail validée de ee.iitm.ac.in - Page d'accueil
Titre
Citée par
Citée par
Année
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ...
2008 Symposium on VLSI Technology, 88-89, 2008
1172008
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ...
2011 IEEE International Electron Devices Meeting (IEDM), 28.1.1 - 28.1.4, 2011
1132011
32nm general purpose bulk CMOS technology for high performance applications at low voltage
F Arnaud, J Liu, YM Lee, KY Lim, S Kohler, J Chen, BK Moon, CW Lai, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
652008
Scaling of 32nm low power SRAM with high-K metal gate
HS Yang, R Wong, R Hasumi, Y Gao, NS Kim, DH Lee, S Badrudduza, ...
Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 1-4, 2008
632008
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
F Arnaud, A Thean, M Eller, M Lipinski, YW Teh, M Ostermayr, K Kang, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
592009
Asymmetric channel MOSFET
X Chen, J Deng, W Li, DR Nair, JE Park, D Tekleab, X Yuan, NS Kim
US Patent 8,237,197, 2012
322012
Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters
DR Nair, S Mahapatra, S Shukuri, JD Bude
IEEE Transactions on Electron Devices 51 (5), 701-707, 2004
272004
Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET
VA Tiwari, D Jaeger, A Scholze, DR Nair
IEEE Transactions on Electron Devices, 61 (5), 1270 - 1277, 2014
172014
CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters
NR Mohapatra, DR Nair, S Mahapatra, V Ramgopal Rao, S Shukuri, ...
Electron Devices, IEEE Transactions on 50 (10), 2104-2111, 2003
172003
Oxygen scavenging spacer for a gate electrode
MP Chudzik, DR Nair, V Narayanan, CJ Radens, JM Shah
US Patent 9,059,211, 2015
152015
Study of the Effect of Surface Roughness on the Performance of RF MEMS Capacitive Switches Through 3-D Geometric Modeling
S Gopalakrishnan, A Dasgupta, DR Nair
IEEE Journal of the Electron Devices Society 4 (6), 451-458, 2016
142016
Novel RF MEMS capacitive switches with design flexibility for multi-frequency operation
S Gopalakrishnan, A DasGupta, DR Nair
Journal of Micromechanics and Microengineering 27 (9), 095013, 2017
132017
Piezoelectric-on-Silicon Array Resonators With Asymmetric Phononic Crystal Tethering
U Rawat, DR Nair, A DasGupta
Journal of Microelectromechanical Systems 26 (4), 773-781, 2017
122017
Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation
DR Nair, S Mahapatra, S Shukuri, JD Bude
IEEE Transactions on Electron Devices 52 (4), 534-540, 2005
102005
Compact Modeling of Proximity Effect in High- Tapered Spiral Inductors
J Sathyasree, V Vanukuru, D Nair, A Chakravorty
IEEE Electron Device Letters 39 (4), 588-590, 2018
92018
New layout dependency in high-k/Metal Gate MOSFETs
M Hamaguchi, D Nair, D Jaeger, H Nishimura, W Li, MH Na, C Bernicot, ...
2011 IEEE International Electron Devices Meeting (IEDM), 25.6.1 - 25.6.4, 2011
82011
Mechanism of drain disturb in SONOS Flash EEPROMs
PB Kumar, R Sharma, PR Nair, DR Nair, S Kamohara, S Mahapatra, ...
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings …, 2005
72005
Spacer protection and electrical connection for array device
JE Park, W Li, DR Nair, MD Sciacca, VY Thean, A Wan, DH Lee, YM Lee
US Patent 8,623,714, 2014
62014
Cycling endurance of NOR Flash EEPROM cells under CHISEL programming operation-impact of technological parameters and scaling
DR Nair, S Shukuri, S Mahapatra
IEEE Transactions on Electron Devices 51 (10), 1672-1678, 2004
62004
Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation
DR Nair, NR Mohapatra, S Mahapatra, S Shukuri, JD Bude
IEEE Transactions on Device and Materials Reliability 4 (1), 32-37, 2004
62004
Le système ne peut pas réaliser cette opération maintenant. Veuillez réessayer plus tard.
Articles 1–20