Dilip Vasudevan
Dilip Vasudevan
Adresse e-mail validée de lbl.gov
Citée par
Citée par
Reversible-logic design with online testability
DP Vasudevan, PK Lala, J Di, JP Parkerson
IEEE transactions on instrumentation and measurement 55 (2), 406-414, 2006
Self-checking carry-select adder design based on two-rail encoding
DP Vasudevan, PK Lala, JP Parkerson
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (12), 2696-2705, 2007
A 6.45Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems
A Roy, A Klinefelter, FB Yahya, X Chen, LP Gonzalez-Guerrero, CJ Lukas, ...
IEEE transactions on biomedical circuits and systems 9 (6), 862-874, 2015
Online testable reversible logic circuit design using NAND blocks
DP Vasudevan, PK Lala, JP Parkerson
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2004
A novel approach for on-line testable reversible logic circuit design
DP Vasudevan, PK Lala, JP Parkerson
13th Asian Test Symposium, 325-330, 2004
A technique for modular design of self-checking carry-select adder
DP Vasudevan, PK Lala
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005
Global built-in self-repair for 3D memories with redundancy sharing and parallel testing
X Wang, D Vasudevan, HHS Lee
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE …, 2011
CMOS realization of online testable reversible logic gates
DP Vasudevan, PK Lala, JP Parkerson
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design …, 2005
10x10: A case study in highly-programmable and energy-efficient heterogeneous federated architecture
AA Chien, T Thanh-Hoang, D Vasudevan, Y Fang, A Shambayati
ACM SIGARCH Computer Architecture News 43 (3), 2-9, 2015
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations
J Chen, D Vasudevan, E Popovici, M Schellekens, P Gillen
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
Generalized pattern matching micro-engine
Y Fang, R ur Rasool, D Vasudevan, AA Chien
4th Workshop on Architectures and Systems for Big Data (ASBD) held with ISCA'14, 2014
Boosted race trees for low energy classification
G Tzimpragos, A Madhavan, D Vasudevan, D Strukov, T Sherwood
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
Ultra low power Booth multiplier using asynchronous logic
J Chen, E Popovici, D Vasudevan, M Schellekens
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems …, 2012
Reversible online BIST using bidirectional BILBO
J Chen, DP Vasudevan, E Popovici, M Schellekens
Proceedings of the 7th ACM international conference on Computing frontiers …, 2010
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder
J Chen, D Vasudevan, E Popovici, M Schellekens
2011 14th Euromicro Conference on Digital System Design, 301-308, 2011
Fault tolerant quantum computation with new reversible gate
DP Vasudevan, PK Lala, JP Parkerson
Proceedings of the NSTI nanotechnology conference, 744-747, 2005
A reversible MIPS multi-cycle control FSM design
D Vasudevan, M Goudarzi, E Popovici, M Schellekens
2009 1st Asia Symposium on Quality Electronic Design, 336-342, 2009
The construction of a fault tolerant reversible gate for quantum computation
DP Vasudevan, PK Lala, JP Parkerson
5th IEEE Conference on Nanotechnology, 2005., 112-115, 2005
The bit-nibble-byte microengine (bnb) for efficient computing on short data
D Vasudevan, AA Chien
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 103-106, 2015
Ultra low power asynchronous charge sharing logic
J Chen, D Vasudevan, M Schellekens, E Popovici
Journal of Low Power Electronics 8 (4), 526-534, 2012
Le système ne peut pas réaliser cette opération maintenant. Veuillez réessayer plus tard.
Articles 1–20