Sangwan Kim
Sangwan Kim
Department of Electrical and Computer Engineering, Ajou University
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Demonstration of L-shaped tunnel field-effect transistors
SW Kim, JH Kim, TJK Liu, WY Choi, BG Park
IEEE transactions on electron devices 63 (4), 1774-1778, 2015
Design guideline of Si-based L-shaped tunneling field-effect transistors
SW Kim, WY Choi, MC Sun, HW Kim, BG Park
Japanese Journal of Applied Physics 51 (6S), 06FE09, 2012
Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery
K Chatterjee, S Kim, G Karbasian, AJ Tan, AK Yadav, AI Khan, C Hu, ...
IEEE Electron Device Letters 38 (10), 1379-1382, 2017
Double-gate TFET with vertical channel sandwiched by lightly doped Si
JH Kim, S Kim, BG Park
IEEE Transactions on Electron Devices 66 (4), 1656-1661, 2019
Tunneling field-effect transistor with Si/SiGe material for high current drivability
HW Kim, JH Kim, SW Kim, MC Sun, E Park, BG Park
Japanese Journal of Applied Physics 53 (6S), 06JE12, 2014
Light effect on negative bias-induced instability of HfInZnO amorphous oxide thin-film transistor
DW Kwon, JH Kim, JS Chang, SW Kim, W Kim, JC Park, CJ Kim, BG Park
IEEE Transactions on electron devices 58 (4), 1127-1133, 2011
Vertical type double gate tunnelling FETs with thin tunnel barrier
JH Kim, SW Kim, HW Kim, BG Park
Electronics Letters 51 (9), 718-720, 2015
An artificial piezotronic synapse for tactile perception
M Kumar, R Singh, H Kang, S Kim, H Seo
Nano Energy 73, 104756, 2020
Effects of localized body doping on switching characteristics of tunnel field-effect transistor (TFET) inverters with vertical structures
DW Kwon, HW Kim, Jang Hyun Kim, E Park, J Lee, W Kim, S Kim, JH Lee, ...
IEEE Transactions on Electron Devices 64 (4), 1799-1805, 2017
Hump effects of germanium / silicon heterojunction tunnel field-effect transistors
SW Kim, WY Choi
IEEE Transactions on Electron Devices 63 (6), 2583-2588, 2016
Investigation on the corner effect of L-shaped tunneling field-effect transistors and their fabrication method
SW Kim, WY Choi, MC Sun, BG Park
Journal of nanoscience and nanotechnology 13 (9), 6376-6381, 2013
Design and fabrication of asymmetric MOSFETs using a novel self-aligned structure
JP Kim, WY Choi, JY Song, SW Kim, JD Lee, BG Park
IEEE Transactions on Electron Devices 54 (11), 2969-2974, 2007
Patterning of Si nanowire array with electron beam lithography for sub-22 nm Si nanoelectronics technology
MC Sun, G Kim, JH Lee, H Kim, SW Kim, HW Kim, JH Lee, H Shin, ...
Microelectronic engineering 110, 141-146, 2013
Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET
Y Choi, K Lee, KY Kim, S Kim, J Lee, R Lee, HM Kim, YS Song, S Kim, ...
Solid-State Electronics 164, 107686, 2020
High on-current Ge-channel heterojunction tunnel field-effect transistor using direct band-to-band tunneling
G Kim, J Lee, JH Kim, S Kim
Micromachines 10 (2), 77, 2019
A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology
AJ Tan, AK Yadav, K Chatterjee, D Kwon, S Kim, C Hu, S Salahuddin
IEEE Electron Device Letters 39 (1), 95-98, 2018
Scalable embedded Ge-junction vertical-channel tunneling field-effect transistor for low-voltage operation
MC Sun, SW Kim, G Kim, HW Kim, JH Lee, H Shin, BG Park
2010 IEEE Nanotechnology Materials and Devices Conference, 286-290, 2010
Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-Voltage Memory Operation
K Chatterjee, S Kim, G Karbasian, D Kwon, AJ Tan, AK Yadav, CR Serrao, ...
IEEE Electron Device Letters 40 (9), 1423-1426, 2019
Investigation on the characteristics of stress-induced hump in amorphous oxide thin film transistors
JH Kim, DW Kwon, JS Chang, SW Kim, JC Park, CJ Kim, BG Park
Applied Physics Letters 99 (7), 043502, 2011
Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field
S Kim, WY Choi
Jpn. J. Appl. Phys 56 (8), 084301, 2017
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