Suman Datta

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Vijaykrishnan NarayananRobert Noll Chair Professor at The Pennsylvania State UniversityAdresse e-mail validée de cse.psu.edu
Marko RadosavljevicIntel CorporationAdresse e-mail validée de intel.com
Sumeet GuptaSchool of Electrical and Computer Engineering, Purdue UniversityAdresse e-mail validée de purdue.edu
Nikhil ShuklaUniversity of VirginiaAdresse e-mail validée de virginia.edu
Kai NiRochester Institute of TechnologyAdresse e-mail validée de rit.edu
Dheeraj MohataSenior Integration Engineer, GCS IncAdresse e-mail validée de gcsincorp.com
Matthew JerryUniversity of Notre Dame / Pennsylvania State UniversityAdresse e-mail validée de nd.edu
Prof. Mantu HudaitAssoc. Prof. of ECE, Virginia Tech; Past: Intel Corporation, Ohio State U, IISc-Bangalore, IIT-KGPAdresse e-mail validée de vt.edu
Arijit RaychowdhuryAssociate Professor, GaTechAdresse e-mail validée de ece.gatech.edu
Xueqing LiAssociate Professor, Tsinghua UniversityAdresse e-mail validée de tsinghua.edu.cn
Huichu LiuIntel Labs, Intel CorporationAdresse e-mail validée de intel.com
Ahmedullah AzizAssistant Professor, University of Tennessee, KnoxvilleAdresse e-mail validée de utk.edu
Darrell G. SchlomCornell UniversityAdresse e-mail validée de cornell.edu
Joshua A. RobinsonProf. MatSE; Center for 2DLM; ATOMIC; 2D Crystal Consort.; The Pennsylvania State UniversityAdresse e-mail validée de psu.edu
Himanshu MadanIntel, PennState UniversityAdresse e-mail validée de intel.com
vinay saripalliPhD in computer Science and Engineering, Penn State UniversityAdresse e-mail validée de psu.edu
Ashish AgrawalDevcie Engineer at Components Research, Intel CorporationAdresse e-mail validée de intel.com
Benjamin GrisafeUniversity of Notre DameAdresse e-mail validée de nd.edu
Theresa MayerPurdue UniversityAdresse e-mail validée de purdue.edu
Ashkar AliIntel CorporationAdresse e-mail validée de psu.edu

Suman Datta

Stinson Chair Professor

Adresse e-mail validée de nd.edu - Page d'accueil

University of Notre Dame


Titre Trier par citations Trier par année Trier par titre	Citée par Citée par	Année
Benchmarking nanotechnology for high-performance and low-power logic transistor applications R Chau, S Datta, M Doczy, B Doyle, B Jin, J Kavalieros, A Majumdar, ... IEEE transactions on nanotechnology 4 (2), 153-158, 2005	814	2005
High-/spl kappa//metal-gate stack and its MOSFET characteristics R Chau, S Datta, M Doczy, B Doyle, J Kavalieros, M Metz IEEE Electron Device Letters 25 (6), 408-410, 2004	661	2004
High performance fully-depleted tri-gate CMOS transistors BS Doyle, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, T Linton, ... IEEE Electron Device Letters 24 (4), 263-265, 2003	621	2003
Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta, SA Hareland US Patent 6,858,478, 2005	469	2005
Integrated nanoelectronics for the future R Chau, B Doyle, S Datta, J Kavalieros, K Zhang Nature materials 6 (11), 810-812, 2007	394	2007
Tri-gate devices and methods of fabrication RS Chau, BS Doyle, J Kavalieros, D Barlage, S Datta US Patent 7,358,121, 2008	389	2008
Two-dimensional gallium nitride realized via graphene encapsulation ZY Al Balushi, K Wang, RK Ghosh, RA Vilá, SM Eichfeld, JD Caldwell, ... Nature materials 15 (11), 1166-1171, 2016	384	2016
Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout B Doyle, B Boyanov, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, ... 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003	351	2003
Atomically thin resonant tunnel diodes built from synthetic van der Waals heterostructures YC Lin, RK Ghosh, R Addou, N Lu, SM Eichfeld, H Zhu, MY Li, X Peng, ... Nature communications 6 (1), 1-6, 2015	305	2015
Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering J Kavalieros, B Doyle, S Datta, G Dewey, M Doczy, B Jin, D Lionberger, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 50-51, 2006	302	2006
Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication SA Hareland, RS Chau, BS Doyle, R Rios, T Linton, S Datta US Patent 7,456,476, 2008	245	2008
A steep-slope transistor based on abrupt electronic phase transition N Shukla, AV Thathachary, A Agrawal, H Paik, A Aziz, DG Schlom, ... Nature communications 6 (1), 1-6, 2015	224	2015
Temperature-Dependent–Characteristics of a VerticalTunnel FET S Mookerjea, D Mohata, T Mayer, V Narayanan, S Datta IEEE Electron Device Letters 31 (6), 564-566, 2010	224	2010
Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication SA Hareland, RS Chau, BS Doyle, R Rios, T Linton, S Datta US Patent 7,820,513, 2010	223	2010
Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate J Kavalieros, A Cappellani, JK Brask, ML Doczy, MV Metz, S Datta, ... US Patent 7,569,443, 2009	223	2009
Nonplanar device with stress incorporation layer and method of fabrication SA Hareland, RS Chau, BS Doyle, S Datta, B Jin US Patent 6,909,151, 2005	218	2005
SRAM and logic transistors with variable height multi-gate transistor architecture S Datta, BS Doyle, JT Kavalieros, Y Wang US Patent App. 11/648,521, 2008	216	2008
Atomic layer deposition of high dielectric constant gate dielectrics M Metz, C Boyd, M Kuhn, S Datta, J Kavalieros, M Doczy, J Brask, R Chau US Patent App. 10/943,693, 2006	211	2006
Transistor Elements for 30nm Physical Gate Lengths and Beyond. B Doyle, R Arghavani, D Barlage, S Datta, M Doczy, J Kavalieros, ... Intel Technology Journal 6 (2), 2002	211	2002
Method and apparatus for improving stability of a 6T CMOS SRAM cell S Datta, BS Doyle, RS Chau, J Kavalieros, B Zheng, SA Hareland US Patent 6,970,373, 2005	204	2005

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