| Approximate adder with hybrid prediction and error compensation technique X Yang, Y Xing, F Qiao, Q Wei, H Yang 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 373-378, 2016 | 17 | 2016 |
| A formal instruction-level GPU model for scalable verification Y Xing, BY Huang, A Gupta, S Malik 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 10 | 2018 |
| Leveraging processor modeling and verification for general hardware modules Y Xing, H Lu, A Gupta, S Malik 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 5 | 2021 |
| Multistage latency adders architecture employing approximate computing X Yang, Y Xing, F Qiao, H Yang Journal of Circuits, Systems and Computers 26 (03), 1750039, 2017 | 4 | 2017 |
| Generalizing tandem simulation: Connecting high-level and RTL simulation models Y Xing, A Gupta, S Malik 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 154-159, 2022 | 3 | 2022 |
| Compositional verification using a formal component and interface specification Y Xing, H Lu, A Gupta, S Malik Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 2 | 2022 |
| SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications H Lu, Y Xing, A Gupta, S Malik ACM Transactions on Design Automation of Electronic Systems 28 (6), 1-24, 2023 | | 2023 |
| Enabling SoC Verification Through Instruction-Level Hardware Models Y Xing Princeton University, 2023 | | 2023 |
| Hardware-Software Interface Specification for Verification in Accelerator-Rich Platforms H Zhang, BY Huang, Y Xing, A Gupta, S Malik | | 2021 |
