| A universal technique for fast and flexible instruction-set architecture simulation A Nohl, G Braun, O Schliebusch, R Leupers, H Meyr, A Hoffmann Proceedings of the 39th annual Design Automation Conference, 22-27, 2002 | 267 | 2002 |
| Architecture exploration for embedded processors with LISA A Hoffmann, H Meyr, R Leupers Kluwer Academic Publishers, 2002 | 246 | 2002 |
| Handbook of signal processing systems SS Bhattacharyya, EF Deprettere, R Leupers, J Takala Springer, 2013 | 244 | 2013 |
| Customizable embedded processors: design technologies and applications P Ienne, R Leupers Elsevier, 2006 | 208 | 2006 |
| Algorithms for address assignment in DSP code generation R Leupers, P Marwedel Proceedings of International Conference on Computer Aided Design, 109-112, 1996 | 206 | 1996 |
| Retargetable code generation based on structural processor description R Leupers, P Marwedel Design Automation for Embedded Systems 3, 75-108, 1998 | 196 | 1998 |
| MAPS: an integrated framework for MPSoC application parallelization J Ceng, J Castrillón, W Sheng, H Scharwächter, R Leupers, G Ascheid, ... Proceedings of the 45th annual Design Automation Conference, 754-759, 2008 | 177 | 2008 |
| Retargetable code generation for digital signal processors R Leupers Springer Science & Business Media, 1997 | 176 | 1997 |
| Code optimization techniques for embedded processors: Methods, algorithms, and tools R Leupers Springer Science & Business Media, 2013 | 167 | 2013 |
| MAPS: Mapping concurrent dataflow applications to heterogeneous MPSoCs J Castrillon, R Leupers, G Ascheid IEEE Transactions on Industrial Informatics 9 (1), 527-545, 2011 | 144 | 2011 |
| Software synthesis and code generation for signal processing systems SS Bhartacharyya, R Leupers, P Marwedel IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000 | 137 | 2000 |
| A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms T Kempf, M Doerper, R Leupers, G Ascheid, H Meyr, T Kogel, ... Design, Automation and Test in Europe, 876-881, 2005 | 127 | 2005 |
| Parameterized posit arithmetic hardware generator R Chaurasiya, J Gustafson, R Shrestha, J Neudorfer, S Nambiar, K Niyogi, ... 2018 IEEE 36th International Conference on Computer Design (ICCD), 334-341, 2018 | 125 | 2018 |
| Retargetable generation of code selectors from HDL processor models R Leupers, P Marwedel Proceedings European Design and Test Conference. ED & TC 97, 140-144, 1997 | 123 | 1997 |
| Instruction scheduling for clustered VLIW DSPs R Leupers Proceedings 2000 International Conference on Parallel Architectures and …, 2000 | 120 | 2000 |
| A SW performance estimation framework for early system-level-design using fine-grained instrumentation T Kempf, K Karuri, S Wallentowitz, G Ascheid, R Leupers, H Meyr Proceedings of the Design Automation & Test in Europe Conference 1, 6 pp., 2006 | 117 | 2006 |
| Code selection for media processors with SIMD instructions R Leupers Proceedings of the conference on Design, automation and test in Europe, 4-8, 2000 | 116 | 2000 |
| System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms A Wieferink, M Doerper, R Leupers, G Ascheid, H Meyr, T Kogel, G Braun, ... IEE Proceedings-Computers and Digital Techniques 152 (1), 3-11, 2005 | 113 | 2005 |
| Retargetable compiler technology for embedded systems: tools and applications R Leupers, P Marwedel Springer Science & Business Media, 2001 | 112 | 2001 |
| Time-constrained code compaction for DSPs R Leupers, P Marwedel Proceedings of the 8th international symposium on System synthesis, 54-59, 1995 | 105 | 1995 |
