Roland Dobai
Roland Dobai
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Towards evolvable systems based on the Xilinx Zynq platform
R Dobai, L Sekanina
2013 IEEE international conference on evolvable systems (ICES), 89-95, 2013
Image filter evolution on the Xilinx Zynq platform
R Dobai, L Sekanina
2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), 164-171, 2013
Low-level flexible architecture with hybrid reconfiguration for evolvable hardware
R Dobai, L Sekanina
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (3), 1-24, 2015
Evolutionary design of hash functions for ip address hashing using genetic programming
M Kidoň, R Dobai
2017 IEEE Congress on Evolutionary Computation (CEC), 1720-1727, 2017
Evolution of non-cryptographic hash function pairs for fpga-based network applications
R Dobai, J Korenek
2015 IEEE Symposium Series on Computational Intelligence, 1214-1219, 2015
Evolutionary design of hash function pairs for network filters
R Dobai, J Korenek, L Sekanina
Applied Soft Computing 56, 173-181, 2017
SAT-based generation of compressed skewed-load tests for transition delay faults
R Dobai, M Balaz
Microprocessors and Microsystems 37 (2), 196-205, 2013
Deductive fault simulation for asynchronous sequential circuits
R Dobai, E Gramatova
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
Delay faults testing
M Baláž, R Dobai, E Gramatová
Design and Test Technology for Dependable Systems-on-Chip, 377-394, 2011
Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays
R Dobai, K Glette, J Torresen, L Sekanina
2014 IEEE International Conference on Evolvable Systems, 85-92, 2014
Adaptive development of hash functions in FPGA-based network routers
R Dobai, J Korenek, L Sekanina
Computational Intelligence (SSCI), 2016 IEEE Symposium Series on, 1-8, 2016
Automated generation of built-in self-repair architectures for random logic soc cores
R Dobai, M Balaz, M Fischerova
2012 15th Euromicro Conference on Digital System Design, 73-78, 2012
Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems
R Dobai
2014 24th International Conference on Field Programmable Logic and …, 2014
Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations
R Dobai, M Baláž
COMPUTING AND INFORMATICS 32 (2), 251-272, 2013
Designing bent boolean functions with parallelized linear genetic programming
J Husa, R Dobai
Proceedings of the Genetic and Evolutionary Computation Conference Companion …, 2017
Genetic method for compressed skewed-load delay test generation
R Dobai, M Balaz
2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012
Test pattern generation for the combinational representation of asynchronous circuits
R Dobai, E Gramatová
13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010
Deductive Fault Simulation Technique for Asynchronous Circuits
R Dobai, E Gramatová
Computing and Informatics 29 (6), 1025-1043, 2012
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques
V Mrazek, L Sekanina, R Dobai, M Sys, P Svenda
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (12 …, 2019
A novel automatic test pattern generator for asynchronous sequential digital circuits
R Dobai, E Gramatová
Microelectronics Journal 42 (3), 501-508, 2011
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