First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs E Capogreco, L Witters, H Arimura, F Sebaai, C Porret, A Hikavyy, R Loo, ...
IEEE Transactions on Electron Devices 65 (11), 5145-5150, 2018
67 2018 First monolithic integration of 3d complementary fet (cfet) on 300mm wafers S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ...
2020 Ieee Symposium on Vlsi Technology, 1-2, 2020
63 2020 Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ...
IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020
32 2020 Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET H Arimura, G Eneman, E Capogreco, L Witters, A De Keersgieter, P Favia, ...
2018 IEEE International Electron Devices Meeting (IEDM), 21.2. 1-21.2. 4, 2018
26 2018 Laser Thermal Anneal of polysilicon channel to boost 3D memory performance JG Lisoni, A Arreghini, G Congedo, M Toledano-Luque, I Toqué-Tresonne, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
25 2014 Analysis of performance/variability trade-off in Macaroni-type 3-D NAND memory G Congedo, A Arreghini, L Liu, E Capogreco, JG Lisoni, K Huet, ...
2014 IEEE 6th International Memory Workshop (IMW), 1-4, 2014
21 2014 Low temperature epitaxial growth of Ge: B and Ge0. 99Sn0. 01: B source/drain for Ge pMOS devices: in-situ and conformal B-doping, selectivity towards oxide and nitride with no … A Vohra, C Porret, D Kohen, S Folkersma, J Bogdanowicz, M Schaekers, ...
Japanese Journal of Applied Physics 58 (SB), SBBA04, 2019
17 2019 Buried power rail integration with Si FinFETs for CMOS scaling beyond the 5 nm node A Gupta, H Mertens, Z Tao, S Demuynck, J Bömmels, G Arutchelvan, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
16 2020 An in-depth study of high-performing strained germanium nanowires pFETs J Mitard, D Jang, G Eneman, H Arimura, B Parvais, O Richard, ...
2018 IEEE Symposium on VLSI Technology, 83-84, 2018
16 2018 Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND A Subirats, A Arreghini, E Capogreco, R Delhougne, CL Tan, A Hikavyy, ...
2017 IEEE International Electron Devices Meeting (IEDM), 21.2. 1-21.2. 4, 2017
16 2017 MOVPE In1− xGaxAs high mobility channel for 3-D NAND memory E Capogreco, JG Lisoni, A Arreghini, A Subirats, B Kunert, W Guo, ...
2015 IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2015
15 2015 Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model R Degraeve, M Toledano-Luque, A Arreghini, B Tang, E Capogreco, ...
2013 IEEE International Electron Devices Meeting, 21.2. 1-21.2. 4, 2013
15 2013 Record GmSAT /SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation H Arimura, D Cott, G Boccardi, R Loo, K Wostyn, L Witters, T Conard, ...
IEEE Transactions on Electron Devices 66 (12), 5387-5392, 2019
14 2019 TEM investigations of gate-all-around nanowire devices P Favia, O Richard, G Eneman, H Mertens, H Arimura, E Capogreco, ...
Semiconductor Science and Technology 34 (12), 124003, 2019
13 2019 High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG E Capogreco, H Arimura, L Witters, A Vohra, C Porret, R Loo, ...
2019 Symposium on VLSI Technology, T94-T95, 2019
13 2019 Feasibility of Inx 1–x As High Mobility Channel for 3-D NAND Memory E Capogreco, A Subirats, JG Lisoni, A Arreghini, B Kunert, W Guo, CL Tan, ...
IEEE Transactions on Electron Devices 64 (1), 130-136, 2016
13 2016 Toward high-performance and reliable Ge channel devices for 2 nm node and beyond H Arimura, E Capogreco, A Vohra, C Porret, R Loo, E Rosseel, A Hikavyy, ...
2020 IEEE International Electron Devices Meeting (IEDM), 2.1. 1-2.1. 4, 2020
12 2020 Understanding the intrinsic reliability behavior of A Chasin, E Bury, J Franco, B Kaczer, M Vandemaele, H Arimura, ...
2018 IEEE International Electron Devices Meeting (IEDM), 34.1. 1-34.1. 4, 2018
12 2018 Integration and electrical evaluation of epitaxially grown Si and SiGe channels for vertical NAND memory applications E Capogreco, R Degraeve, JG Lisoni, V Luong, A Arreghini, ...
2015 IEEE International Memory Workshop (IMW), 1-4, 2015
10 2015 Integration and electrical evaluation of epitaxially grown Si and SiGe channels for vertical NAND memory applications E Capogreco, R Degraeve, JG Lisoni, V Luong, A Arreghini, ...
2015 IEEE International Memory Workshop (IMW), 1-4, 2015
10 2015 