| Graph-based transistor network generation method for supergate design VN Possani, V Callegaro, AI Reis, RP Ribas, F de Souza Marques, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 692-705, 2015 | 41 | 2015 |
| Optimizing transistor networks using a graph-based technique VN Possani, RS de Souza, JS Domingues, LV Agostini, FS Marques, ... Analog Integrated Circuits and Signal Processing 73, 841-850, 2012 | 16 | 2012 |
| Memory bandwidth reduction in video coding systems through context adaptive lossless reference frame compression D Silveira, G Sanchez, M Grellert, V Possani, L Agostini 2012 VIII Southern Conference on Programmable Logic, 1-6, 2012 | 13 | 2012 |
| Unlocking fine-grain parallelism for AIG rewriting V Possani, YS Lu, A Mishchenko, K Pingali, R Ribas, A Reis 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 11 | 2018 |
| SAT-sweeping enhanced for logic synthesis L Amarú, F Marranghello, E Testa, C Casares, V Possani, J Luo, P Vuillod, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 9 | 2020 |
| LUT-based optimization for ASIC design flow L Amarú, V Possani, E Testa, F Marranghello, C Casares, J Luo, P Vuillod, ... 2021 58th ACM/IEEE Design Automation Conference (DAC), 871-876, 2021 | 7 | 2021 |
| Improving the methodology to build non-series-parallel transistor arrangements VN Possani, V Callegaro, AI Reis, RP Ribas, FS Marques, LS da Rosa 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013 | 7 | 2013 |
| Parallel combinational equivalence checking VN Possani, A Mishchenko, RP Ribas, AI Reis IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 6 | 2019 |
| NSP kernel finder-A methodology to find and to build non-series-parallel transistor arrangements VN Possani, FS Marques, LS da Rosa Junior, V Callegaro, AI Reis, ... 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012 | 6 | 2012 |
| Majority-based design flow for AQFP superconducting family G Meuli, V Possani, R Singh, SY Lee, AT Calvino, DS Marakkalage, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 34-39, 2022 | 5 | 2022 |
| Exact benchmark circuits for logic synthesis WL Neto, VN Possani, FS Marranghello, JM Matos, PE Gaillardon, AI Reis, ... IEEE Design & Test 37 (3), 51-58, 2019 | 5 | 2019 |
| Exploring independent gates in FinFET-based transistor network generation VN Possani, AI Reis, RP Ribas, FS Marques, LS da Rosa Junior Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 1-6, 2014 | 5 | 2014 |
| Improving LUT-based optimization for ASICs WL Neto, L Amarú, V Possani, P Vuillod, J Luo, A Mishchenko, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 421-426, 2022 | 4 | 2022 |
| High throughput 4x4 and 8x8 SATD similarity criteria architectures for video coding applications JS Dominges Jr, VN Possani, DS Silveira, LS da Rosa Jr, LV Agostini 2011 VII Designer Forum (DF), 115, 2011 | 4 | 2011 |
| Transistor-level optimization of CMOS complex gates VN Possani, FS Marques, LS da Rosa Junior, V Callegaro, AI Reis, ... 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2013 | 3 | 2013 |
| Transistor networks design using a graph-based approach VN Possani, EF Timm, LV Agostini, LS Da Rosa Junior 10th Microelectronics Students Forum, 2010 | 3 | 2010 |
| Parallel algorithms for scalable logic synthesis & verification VN Possani | 2 | 2019 |
| Transistor count optimization in IG FinFET network design VN Possani, AI Reis, RP Ribas, FS Marques, LS da Rosa IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 2 | 2016 |
| Efficient transistor-level design of CMOS gates VN Possani, V Callegaro, AI Reis, RP Ribas, FS Marques, ... Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 2 | 2013 |
| Decreasing transistor count using an edges sharing technique in a graph structure VN Possani, LV Agostini, FS Marques, LS Da Rosa Proc. SIM 26th South Symp. Microelectron, 2011 | 2 | 2011 |
