Pierre Morin
Pierre Morin
Adresse e-mail validée de imec.be
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Nickel vs. Cobalt Silicide integration for sub-50nm CMOS
B Froment, M Muller, H Brut, R Pantel, V Carron, H Achard, A Halimaoui, ...
ESSDERC'03. 33rd Conference on European Solid-State Device Research, 2003 …, 2003
Passivation issues in Active Pixel CMOS Image Sensors
J Regolini, D Benoit, P Morin
WODIM, Workshop on Dielectrics in Microelectronics, 2006
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
Q Liu, M Vinet, J Gimbert, N Loubet, R Wacquez, L Grenouillet, Y Le Tiec, ...
2013 IEEE International Electron Devices Meeting, 9.2. 1-9.2. 4, 2013
Defect-free strain relaxed buffer layer
P Morin, K Cheng, J Fronheiser, X Cai, J Li, S Mochizuki, R Xie, H He, ...
US Patent App. 14/588,221, 2016
A functional 0.69/spl mu/m/sup 2/embedded 6T-SRAM bit cell for 65 nm CMOS platform
F Arnaud, F Boeuf, F Salvetti, D Lenoble, F Wacquant, C Regnier, P Morin, ...
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003
Stress memorization technique (SMT) optimization for 45nm CMOS
C Ortolland, P Morin, C Chaton, E Mastromatteo, C Populaire, S Orain, ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 78-79, 2006
Hydrogen desorption and diffusion in PECVD silicon nitride. Application to passivation of CMOS active pixel sensors
D Benoit, J Regolini, P Morin
INFOS, Conference of Insulating Films on Semiconductors, 2007
A conventional 45nm CMOS node low-cost platform for general purpose and low power applications
F Boeuf, F Arnaud, MT Basso, D Sotta, F Wacquant, J Rosa, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
Low cost 65nm cmos platform for low power & general purpose applications
F Arnaud, B Duriez, B Tavel, L Pain, J Todeschini, M Jurdit, Y Laplanche, ...
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 10-11, 2004
Three dimensional imaging and analysis of a single nano-device at the ultimate scale using correlative microscopy techniques
A Grenier, S Duguay, JP Barnes, R Serra, N Rolland, G Audoit, P Morin, ...
Applied Physics Letters 106 (21), 213102, 2015
A comparison of the mechanical stability of silicon nitride films deposited with various techniques
P Morin, G Raymond, D Benoit, P Maury, R Beneyton
Applied surface science 260, 69-72, 2012
Tensile contact etch stop layer for nMOS performance enhancement: influence of the film morphology
P Morin, C Chaton, C Reddy, C Ortolland, MT Basso, F Arnaud
ECS meeting, May, 2005
Method to induce strain in finFET channels from an adjacent region
P Morin, N Loubet
US Patent 9,099,559, 2015
0.248/spl mu/m/sup 2/and 0.334/spl mu/m/sup 2/conventional bulk 6T-SRAM bit-cells for 45nm node low cost-general purpose applications
F Boeuf, F Arnaud, C Boccaccio, F Salvetti, J Todeschini, L Pain, M Jurdit, ...
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 130-131, 2005
Method to induce strain in 3-D microfabricated structures
N Loubet, P Morin
US Patent 8,952,420, 2015
Atomic-scale redistribution of dopants in polycrystalline silicon layers
S Duguay, A Colin, D Mathiot, P Morin, D Blavette
Journal of Applied Physics 108 (3), 034911, 2010
FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node
Q Liu, P ...Morin, ...
IEDM, 2014
Multi-layer strained channel FinFET
P Morin, N Loubet
US Patent 9,660,080, 2017
Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate
P Morin
US Patent 9,236,474, 2016
UTBB FDSOI scaling enablers for the 10nm node
L Grenouillet, Q Liu, R Wacquez, P Morin, N Loubet, D Cooper, A Pofelski, ...
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2013
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