| A boundary scan test controller for hierarchical BIST JS Matos, FS Pinto, JMM Ferreira Test Conference, 1992. Proceedings., International, 217, 1995 | 38 | 1995 |
| A boundary scan test controller for hierarchical BIST JMM Ferreira, FS Pinto, JS Matos Proceedings of the IEEE International Test Conference on Discover the New …, 1992 | 38* | 1992 |
| Control and observation of analog nodes in mixed-signal boards JS Matos, AC Leão, JC Ferreira Test Conference, 1993. Proceedings., International, 323-331, 1993 | 34 | 1993 |
| Cross-correlation between iDD and vOUT signals for testing analogue circuits JM da Silva, JS Matos, IM Bell, GE Taylor Electronics Letters 31 (19), 1617-1618, 1995 | 20 | 1995 |
| Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits JM Da Silva, JS Matos, IM Bell, GE Taylor Journal of Electronic Testing 9 (1-2), 75-88, 1996 | 16 | 1996 |
| Automatic generation of a single-chip solution for board-level BIST of boundary scan boards JMM Ferreira, JS Matos, FS Pinto Design Automation, 1992. Proceedings.,[3rd] European Conference on, 154-158, 1992 | 15 | 1992 |
| Boundary scan test, test methodology, and fault modeling F De Jong, JS Matos, JM Ferreira Journal of Electronic Testing 2 (1), 77-88, 1991 | 15 | 1991 |
| Binary decision diagrams: From abstract representations to physical implementations JS Matos, JV Oldfield Proceedings of the 20th Design Automation Conference, 567-570, 1983 | 14 | 1983 |
| RVC - A Reconfigurable Coprocessor for Vector Processing Applications JC Alves, JS Matos Proceedings of the IEEE Symposium on Field-Programmable Custom Computing …, 1998 | 13 | 1998 |
| A comparison of ADC dynamic test methods HS Mendonça, JM Silva, JS Matos Proc. Design of Circuits and Integrated Systems Conference, 102-107, 2000 | 11 | 2000 |
| Evaluation of i DD/v OUT cross-correlation for mixed current-voltage testing of analogue and mixed-signal circuits JM Da Silva, JS Matos European Design and Test Conference, 1996. ED&TC 96. Proceedings, 264-268, 1996 | 10 | 1996 |
| Scalable hardware architecture for disparity map computation and object location in real-time PM Santos, JC Ferreira, JS Matos Journal of Real-Time Image Processing, 1-13, 2013 | 7 | 2013 |
| Design for Embedded Testing of an LNA JM da Silva, A Pinho, JS Matos XX Design of Circuits and Integrated Systems, 2005 | 6 | 2005 |
| Functional in-circuit characterisation of ΣΔ modulators JM da Silva, JS Duarte, JS Matos Measurement 32 (4), 257-264, 2002 | 6 | 2002 |
| ADC testing using joint time–frequency analysis H Mendonça, JM da Silva, JS Matos Computer Standards & Interfaces 23 (2), 129-135, 2001 | 6 | 2001 |
| Architecture of test support ICs for mixed-signal testing JS Matos, JC Ferreira, AC Leão, JM Silva VLSI Test Symposium, 1994. Proceedings., 12th IEEE, 240-246, 1994 | 6 | 1994 |
| Mixed-signal BIST using correlation and reconfigurable hardware JM da Silva, JS Duarte, JS Matos Design, Automation and Test in Europe Conference and Exhibition 2000 …, 2000 | 5 | 2000 |
| A simulated annealing approach for high-level synthesis with reconfigurable functional units JC Alves, JS Matos Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest …, 1995 | 5 | 1995 |
| A modular architecture for BIST of boundary scan boards JMM Ferreira, FS Pinto, JS Matos Euro ASIC'92, Proceedings., 184-188, 1992 | 5 | 1992 |
| Computing ADC harmonic content from a reduced number of values HS Mendonça, JM da Silva, JS Matos Instrumentation and Measurement Technology Conference, 2003. IMTC'03 …, 2003 | 4 | 2003 |
