| Methodology for 3-D substrate network extraction for spice simulation of parasitic currents in smart power ICs P Buccella, C Stefanucci, H Zou, Y Moursy, R Iskander, JM Sallese, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 27 | 2015 |
| Automatic DC operating point computation and design plan generation for analog IPs R Iskander, MM Louërat, A Kaiser Analog Integrated Circuits and Signal Processing 56, 93-105, 2008 | 27 | 2008 |
| A python-based layout-aware analog design methodology for nanometric technologies S Youssef, F Javid, D Dupuis, R Iskander, MM Louerat 2011 IEEE 6th International Design and Test Workshop (IDT), 62-67, 2011 | 26 | 2011 |
| Hierarchical sizing and biasing of analog firm intellectual properties R Iskander, MM Louërat, A Kaiser Integration 46 (2), 172-188, 2013 | 24 | 2013 |
| Synthesis of CMOS analog cells using AMIGO R Iskander, M Dessouky, M Aly, M Magdy, N Hassan, N Soliman, ... 2003 Design, Automation and Test in Europe Conference and Exhibition, 297 …, 2003 | 23 | 2003 |
| Simulation-based hierarchical sizing and biasing of analog firm IPs F Javid, R Iskander, MM Louërat 2009 IEEE Behavioral Modeling and Simulation Workshop, 43-48, 2009 | 18 | 2009 |
| Design space exploration for analog IPs using CAIRO+ R Iskander, L De Lamarre, A Kaiser, MM Louërat IEEE International Conference on Electrical Electronic and Computer …, 2004 | 18 | 2004 |
| Analog circuits sizing using bipartite graphs F Javid, R Iskander, MM Louërat, D Dupuis 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 15 | 2011 |
| Substrate noise modeling with dedicated CAD framework for smart power ICs H Zou, Y Moursy, R Iskander, C Stefanucci, P Buccella, M Kayal, ... 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1554-1557, 2015 | 12 | 2015 |
| A novel CAD framework for substrate modeling H Zou, Y Moursy, R Iskander, MM Louërat, JP Chaput 2014 10th Conference on Ph. D. Research in Microelectronics and Electronics …, 2014 | 12 | 2014 |
| Method for automated assistance to design nonlinear analog circuit with transient solver R Iskander, MM Louerat, A Kaiser, F Javid US Patent 9,898,566, 2018 | 10 | 2018 |
| Enriching UVM in SystemC with AMS extensions for randomization and coverage T Vörtler, T Klotz, K Einwich, Y Li, Z Wang, MM Louërat, JP Chaput, ... Design and Verification Conference and Exhibition (DVCON Europe), 2014 | 10 | 2014 |
| Hierarchical graph-based sizing for analog cells through reference transistors R Iskander, MM Louërat, A Kaiser 2006 Ph. D. Research in Microelectronics and Electronics, 321-324, 2006 | 10 | 2006 |
| AUTOMICS: A novel approach for substrate modeling for Automotive applications Y Moursy, S Afara, P Buccella, C Stefanucci, R Iskander, M Kayal, ... 18th IEEE European Test Symposium, 2013 | 8 | 2013 |
| Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs Y Moursy, H Zou, R Iskander, P Tisserand, DM Ton, G Pasetti, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 265-268, 2016 | 7 | 2016 |
| Automatic stress effects computation based on a layout generation tool for analog IC S Youssef, D Dupuis, R Iskander, MM Louerat 2010 IEEE International Behavioral Modeling and Simulation Workshop, 7-12, 2010 | 7 | 2010 |
| Efficient substrate noise coupling verification and failure analysis methodology for smart power ICs in automotive applications Y Moursy, H Zou, R Khalil, R Iskander, P Tisserand, DM Ton, G Pasetti, ... IEEE Transactions on Power Electronics 32 (7), 5550-5559, 2016 | 6 | 2016 |
| Analog circuits sizing using the fixed point iteration algorithm with transistor compact models F Javid, R Iskander, F Durbin, MM Louërat Proceedings of the 19th International Conference Mixed Design of Integrated …, 2012 | 6 | 2012 |
| Knowledge-aware synthesis for analog integrated circuit design and reuse R Iskander Dissertation, University Pierre et Marie Curie, Paris VI, 2008 | 6 | 2008 |
| Knowledge-aware synthesis using hierarchical graph-based sizing and biasing R Iskander, D Galayko, MM Louërat, A Kaiser 2007 IEEE Northeast Workshop on Circuits and Systems, 984-987, 2007 | 6 | 2007 |
Yasser MoursySenior research engineer at CEA LETIAdresse e-mail validée de cea.fr
