L Entrena
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Autonomous fault emulation: A new FPGA-based acceleration system for hardness evaluation
C Lopez-Ongil, M Garcia-Valderas, M Portela-Garcia, L Entrena
IEEE Transactions on Nuclear Science 54 (1), 252-261, 2007
1472007
Combinational and sequential logic optimization by redundancy addition and removal
LA Entrena, KT Cheng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
1471995
Multi-level logic optimization by redundancy addition and removal
KT Cheng, LA Entrena
1993 European Conference on Design Automation with the European Event in …, 1993
1211993
Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection
L Entrena, M Garcia-Valderas, R Fernandez-Cardenal, A Lindoso, ...
IEEE Transactions on Computers 61 (3), 313-322, 2010
1092010
Sequential logic optimization by redundancy addition and removal
L Entrena, KT Cheng
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD …, 1993
1031993
New techniques for speeding-up fault-injection campaigns
L Berrojo, I González, F Corno, MS Reorda, G Squillero, L Entrena, ...
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
942002
Using benchmarks for radiation testing of microprocessors and FPGAs
H Quinn, WH Robinson, P Rech, M Aguirre, A Barnard, M Desogus, ...
IEEE Transactions on Nuclear Science 62 (6), 2547-2554, 2015
512015
Analyzing the impact of single-event-induced charge sharing in complex circuits
S Pagliarini, F Kastensmidt, L Entrena, A Lindoso, E San Millan
IEEE Transactions on Nuclear Science 58 (6), 2768-2775, 2011
492011
AKARI-X: A pseudo random number generator for secure lightweight systems
H Martin, E San Millan, L Entrena, PPC Lopez
IOLTS, 13-15, 2011
47*2011
A unified environment for fault injection at any design level based on emulation
C Lopez-Ongil, L Entrena, M Garcia-Valderas, M Portela, MA Aguirre, ...
IEEE Transactions on Nuclear Science 54 (4), 946-950, 2007
432007
High performance FPGA-based image correlation
A Lindoso, L Entrena
Journal of Real-Time Image Processing 2 (4), 223-233, 2007
422007
An industrial environment for high-level fault-tolerant structures insertion and validation
L Berrojo, F Corno, L Entrena, I González, C Lopez, MS Reorda, ...
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 229-236, 2002
412002
SET emulation considering electrical masking effects
L Entrena, MG Valderas, RF Cardenal, MP Garcia, CL Ongil
IEEE Transactions on Nuclear Science 56 (4), 2021-2025, 2009
362009
Fault injection in modern microprocessors using on-chip debugging infrastructures
M Portela-Garcia, C Lopez-Ongil, MG Valderas, L Entrena
IEEE Transactions on Dependable and Secure Computing 8 (2), 308-314, 2010
352010
Constrained placement methodology for reducing SER under single-event-induced charge sharing effects
L Entrena, A Lindoso, E San Millan, S Pagliarini, F Almeida, ...
IEEE Transactions on Nuclear Science 59 (4), 811-817, 2012
332012
A rapid fault injection approach for measuring seu sensitivity in complex processors
M Portela-Garcia, C Lopez-Ongil, M Garcia-Valderas, L Entrena
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 101-106, 2007
332007
Correlation-based fingerprint matching with orientation field alignment
A Lindoso, L Entrena, J Liu-Jimenez, E San Millan
International Conference on Biometrics, 713-721, 2007
322007
On the use of embedded debug features for permanent and transient fault resilience in microprocessors
M Portela-García, M Grosso, M Gallardo-Campos, MS Reorda, L Entrena, ...
Microprocessors and Microsystems 36 (5), 334-343, 2012
282012
Correlation-based fingerprint matching using FPGAs
A Lindoso, L Entrena, C López-Ongil, J Liu
Proceedings. 2005 IEEE International Conference on Field-Programmable …, 2005
282005
Timing optimization by an improved redundancy addition and removal technique
LA Entrena, JA Espejo, E Olías, J Uceda
Proceedings EURO-DAC'96. European Design Automation Conference with EURO …, 1996
271996
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