Edson Ifarraguirre Moreno
Edson Ifarraguirre Moreno
Professor of Computer Science, PUCRS
Adresse e-mail validée de pucrs.br - Page d'accueil
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Comparison of network-on-chip mapping algorithms targeting low energy consumption
CAM Marcon, EI Moreno, NLV Calazans, FG Moraes
IET Computers & Digital Techniques 2 (6), 471-482, 2008
762008
From VHDL register transfer level to SystemC transaction level modeling: a comparative case study
N Calazans, E Moreno, F Hessel, V Rosa, F Moraes, E Carara
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
612003
Evaluation of algorithms for low energy mapping onto NoCs
CAM Marcon, EI Moreno, NLV Calazans, FG Moraes
2007 IEEE International Symposium on Circuits and Systems, 389-392, 2007
272007
CAFES: A framework for intrachip application modeling and communication architecture design
C Marcon, N Calazans, E Moreno, F Moraes, F Hessel, A Susin
Journal of Parallel and Distributed Computing 71 (5), 714-728, 2011
182011
Arbitration and routing impact on NoC design
EI Moreno, CAM Marcon, NLV Calazans, FG Moraes
2011 22nd IEEE International Symposium on Rapid System Prototyping, 193-198, 2011
162011
Topological impact on latency and throughput: 2D versus 3D NoC comparison
Y Ghidini, T Webber, E Moreno, I Quadros, R Fagundes, C Marcon
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012
122012
Buffer depth and traffic influence on 3D NoCs performance
Y Ghidini, T Webber, E Moreno, F Grando, R Fagundes, C Marcon
2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), 9-15, 2012
112012
Integrating abstract NoC models within MPSoC design
EI Moreno, KM Popovici, NLV Calazans, AA Jerraya
2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping …, 2008
112008
MoNoC: A monitored network on chip with path adaptation mechanism
E Moreno, T Webber, C Marcon, F Moraes, N Calazans
Journal of Systems Architecture 60 (10), 783-795, 2014
52014
Test time reduction reusing multiple processors in a network-on-chip based architecture
AM Amory, M Lubaszewski, FG Moraes, EI Moren
Design, Automation and Test in Europe, 62-63, 2005
52005
Determining the test sources/sinks for NoC TAMs
A Amory, E Moreno, F Moraes, MS Lubaszewski
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 8-13, 2013
42013
Modelagem e descrição de socs em diferentes níveis de abstração
EI Moreno, TR Ares, NLV Calazans
X Workshop Iberchip, Cartagena, 1-11, 2004
42004
Mapeamento e adaptação de rotas de comunicação em redes em chip
EI Moreno
Pontifícia Universidade Católica do Rio Grande do Sul, 2010
32010
Modelagem, Descrição e Validação de Redes Intrachip no Nível de Transação
EI Moreno
Dissertação de Mestrado, PPGCC-FACIN-PUCRS, 2004
22004
A monitored NoC with runtime path adaptation
E Moreno, T Webber, C Marcon, F Moraes, N Calazans
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1965-1968, 2014
12014
Evaluation of adaptive management techniques in NoC-Based MPSoCs
FG Moraes, EA Carara, M Ruaro, GA Madalozzo
2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012
12012
Sistemas operacionais
E Moreno
Dissertação de M estrado. Departamento de Informática. PUC-Rio, 2002
12002
Gerador de números pseudo-aleatórios de consumo reduzido
J Leao da Silva Jr, J Costa, G Rohde, E Moreno, R Soares, F Moller
BR Patent App. 10 2015 028898 0, 2015
2015
Determining the test sources/sinks for NoC TAMs
A de Morais Amory, E MORENO, F MORAES, MS LUBASZEWSKI
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013 …, 2013
2013
LÓGICA PARA COMPUTAÇÃO
EI MORENO
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