| On the farthest line-segment Voronoi diagram E Papadopoulou, SK Dey International Journal of Computational Geometry & Applications 23 (06), 443-459, 2013 | 31 | 2013 |
| The L_infinity (L_1) Farthest Line-Segment Voronoi Diagram SK Dey, E Papadopoulou 2012 Ninth International Symposium on Voronoi Diagrams in Science and …, 2012 | 8 | 2012 |
| Topology and context-based pattern extraction using line-segment Voronoi diagram SK Dey, P Cheilaris, N Casati, M Gabrani, E Papadopoulo Design-Process-Technology Co-optimization for Manufacturability IX 9427, 42-56, 2015 | 5 | 2015 |
| Implementing the L ∞ Segment Voronoi Diagram in CGAL and Applying in VLSI Pattern Analysis P Cheilaris, SK Dey, M Gabrani, E Papadopoulou Mathematical Software–ICMS 2014: 4th International Congress, Seoul, South …, 2014 | 5 | 2014 |
| Layout pattern analysis using the Voronoi diagram of line segments SK Dey, P Cheilaris, M Gabrani, E Papadopoulou Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (1), 013504, 2016 | 2 | 2016 |
| Voronoi diagrams in the max-norm: Algorithms, implementation, and applications SK Dey Università della Svizzera italiana, 2015 | 1 | 2015 |
| Test pattern generation for droop faults D Mitra, S Sur-Kolay, BB Bhattacharya, S Kundu, A Nigam, SK Dey IET Computers & Digital Techniques 4 (4), 274-284, 2010 | 1 | 2010 |
| Voronoi Diagrams in the L∞ metric and VLSI Applications SK Dey | | 2010 |
| Analysis of data structures for VLSI tools SK Dey PQDT-Global, 2009 | | 2009 |
| An Efficient Simulator for Power-grid Analysis in VLSI Chips I Vishnuvardhan, SK Dey, BBB Susmita Sur-Kolay, Debasis Mitra Proceedings of the International Conference on Modeling and Simulation (MS’07), 2007 | | 2007 |
| Testing Droop Faults in Full Scan Circuits D Mitra, A Nigam, SK Dey, S Sur-Kolay, BB Bhattacharya Proceedings of the VLSI Design and Test Symposium (VDAT 2007), 185-195, 2007 | | 2007 |
| Voronoi Diagrams in L∞-for VLSI Critical Area Computation SK Dey, E Papadopoulou | | |
| Implementing the L∞ segment Voronoi diagram in CGAL and an application in VLSI pattern analysis P Cheilaris, SK Dey, M Gabrani, E Papadopoulou | | |
Evanthia PapadopoulouFaculty of Informatics, Università della Svizzera italiana, Lugano, SwitzerlandVerified email at usi.ch
