Fazal Hameed
Fazal Hameed
Post-doc at TU-Dresden
Adresse e-mail validée de tu-dresden.de - Page d'accueil
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Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
F Hameed, L Bauer, J Henkel
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
322013
Reducing latency in an SRAM/DRAM cache hierarchy via a novel tag-cache architecture
F Hameed, L Bauer, J Henkel
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
212014
Design of high performance fpga based face recognition system
I Sajid, MM Ahmed, I Taj, M Humayun, F Hameed
Progress in Electromagnetic Research Symposium Proceeding, 504-510, 2008
182008
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores
F Hameed, L Bauer, J Henkel
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 77-82, 2013
172013
Dynamic thermal management in 3D multi-core architecture through run-time adaptation
F Hameed, MA Al Faruque, J Henkel
2011 Design, Automation & Test in Europe, 1-6, 2011
172011
Performance and energy-efficient design of STT-RAM last-level cache
F Hameed, AA Khan, J Castrillon
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (6 …, 2018
152018
Dynamic cache management in multi-core architectures through run-time adaptation
F Hameed, L Bauer, J Henkel
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 485-490, 2012
142012
Architecting STT Last-Level-Cache for performance and energy improvement
F Hameed, MB Tahoori
2016 17th International Symposium on Quality Electronic Design (ISQED), 319-324, 2016
112016
Architecting on-chip DRAM cache for simultaneous miss rate and latency reduction
F Hameed, L Bauer, J Henkel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
112015
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache
F Hameed, L Bauer, J Henkel
2013 International Conference on Hardware/Software Codesign and System …, 2013
112013
RTSim: A cycle-accurate simulator for racetrack memories
AA Khan, F Hameed, R Bläsing, S Parkin, J Castrillon
IEEE Computer Architecture Letters 18 (1), 43-46, 2019
92019
VAET-STT: Variation aware STT-MRAM analysis and design space exploration tool
SM Nair, R Bishnoi, MS Golanbari, F Oboril, F Hameed, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
72017
Efficient STT-RAM last-level-cache architecture to replace DRAM cache
F Hameed, C Menard, J Castrillon
Proceedings of the International Symposium on Memory Systems, 141-151, 2017
72017
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization
F Hameed, J Castrillon
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
72017
Shiftsreduce: Minimizing shifts in racetrack memory 4.0
AA Khan, F Hameed, R Bläsing, SSP Parkin, J Castrillon
ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-23, 2019
52019
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads
AA Khan, NA Rink, F Hameed, J Castrillon
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on …, 2019
52019
Normally-off stt-mram cache with zero-byte compression for energy efficient last-level caches
F Oboril, F Hameed, R Bishnoi, A Ahari, H Naeimi, M Tahoori
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
52016
SHRIMP: Efficient instruction delivery with domain wall memory
J Multanen, P Jääskeläinen, AA Khan, F Hameed, J Castrillon
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
42019
Nvmain extension for multi-level cache systems
AA Khan, F Hameed, J Castrillon
Proceedings of the Rapido'18 Workshop on Rapid Simulation and Performance …, 2018
22018
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement
F Hameed, J Castrillon
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (10 …, 2019
12019
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