Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering KK Bhuwalka, J Schulze, I Eisele
IEEE transactions on electron devices 52 (5), 909-917, 2005
395 2005 Vertical tunnel field-effect transistor KK Bhuwalka, S Sedlmaier, AK Ludsteck, C Tolksdorf, J Schulze, I Eisele
IEEE Transactions on Electron Devices 51 (2), 279-282, 2004
329 2004 Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer KK Bhuwalka, J Schulze, I Eisele
Japanese Journal of Applied Physics 43 (7R), 4073, 2004
282 2004 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications G Bae, DI Bae, M Kang, SM Hwang, SS Kim, B Seo, TY Kwon, TJ Lee, ...
2018 IEEE International Electron Devices Meeting (IEDM), 28.7. 1-28.7. 4, 2018
227 2018 A simulation approach to optimize the electrical parameters of a vertical tunnel FET KK Bhuwalka, J Schulze, I Eisele
IEEE transactions on electron devices 52 (7), 1541-1547, 2005
173 2005 Fabrication and Analysis of a AM Walke, A Vandooren, R Rooyackers, D Leonelli, A Hikavyy, R Loo, ...
IEEE Transactions on Electron Devices 61 (3), 707-715, 2014
143 2014 P-channel tunnel field-effect transistors down to sub-50 nm channel lengths KK Bhuwalka, M Born, M Schindler, M Schmidt, T Sulima, I Eisele
Japanese journal of applied physics 45 (4S), 3106, 2006
131 2006 Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- M Schlosser, KK Bhuwalka, M Sauter, T Zilbauer, T Sulima, I Eisele
IEEE transactions on electron devices 56 (1), 100-108, 2008
119 2008 Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling KK Bhuwalka, KI Goto
US Patent 7,812,370, 2010
92 2010 Demonstration of scaled Ge p-channel FinFETs integrated on Si MJH Van Dal, G Vellianitis, G Doornbos, B Duriez, TM Shen, CC Wu, ...
2012 International Electron Devices Meeting, 23.5. 1-23.5. 4, 2012
85 2012 Tunnel FET: A CMOS device for high temperature applications M Born, KK Bhuwalka, M Schindler, U Abelein, M Schmidt, T Sulima, ...
2006 25th international conference on microelectronics, 124-127, 2006
76 2006 Tunnel field-effect transistors with superlattice channels KK Bhuwalka, CY Wang, KI Goto, WC Lee, CH Diaz
US Patent 7,834,345, 2010
65 2010 Improved reliability by reduction of hot-electron damage in the vertical impact-ionization MOSFET (I-MOS) U Abelein, M Born, KK Bhuwalka, M Schindler, M Schlosser, T Sulima, ...
IEEE electron device letters 28 (1), 65-67, 2006
65 2006 Semiconductor device KK Bhuwalka, SJ Kim, JC Kim, H Kim
US Patent 10,217,816, 2019
61 2019 An ultralow-resistance ultrashallow metallic source/drain contact scheme for III–V NMOS R Oxland, SW Chang, X Li, SW Wang, G Radhakrishnan, W Priyantha, ...
IEEE electron device letters 33 (4), 501-503, 2012
60 2012 Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers B Duriez, G Vellianitis, MJH Van Dal, G Doornbos, R Oxland, ...
2013 IEEE International Electron Devices Meeting, 20.1. 1-20.1. 4, 2013
58 2013 InAs N-MOSFETs with record performance of Ion = 600 μA/μm at Ioff = 100 nA/μm (Vd = 0.5 V) SW Chang, X Li, R Oxland, SW Wang, CH Wang, R Contreras-Guerrero, ...
2013 IEEE International Electron Devices Meeting, 16.1. 1-16.1. 4, 2013
47 2013 A novel vertical impact ionisation MOSFET (I-MOS) concept U Abelein, M Born, KK Bhuwalka, M Schindler, M Schmidt, T Sulima, ...
2006 25th International Conference on Microelectronics, 121-123, 2006
43 2006 Tunnel FET and methods for forming the same KK Bhuwalka, G Doornbos, M Passlack
US Patent 8,471,329, 2013
39 2013 InAs hole inversion and bandgap interface state density of 2× 1011 cm− 2 eV− 1 at HfO2/InAs interfaces CH Wang, SW Wang, G Doornbos, G Astromskas, K Bhuwalka, ...
Applied Physics Letters 103 (14), 2013
38 2013 
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