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Vikram Arkalgud Chandrasetty
Vikram Arkalgud Chandrasetty
Western Digital Corporation, India
Verified email at ieee.org - Homepage
Title
Cited by
Cited by
Year
FPGA implementation of a LDPC decoder using a reduced complexity message passing algorithm
VA Chandrasetty, SM Aziz
Journal of Networks 6 (1), 36-45, 2011
512011
FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm
VA Chandrasetty, SM Aziz
Computer Research and Development, 2010 Second International Conference on …, 2010
492010
An area efficient LDPC decoder using a reduced complexity min-sum algorithm
VA Chandrasetty, SM Aziz
Integration, the VLSI Journal 45 (2), 141-148, 2012
442012
Resource efficient LDPC decoders for multimedia communication
VA Chandrasetty, SM Aziz
INTEGRATION, the VLSI journal 48, 213-220, 2015
282015
VLSI Design: A Practical Guide for FPGA and ASIC Implementations
VA Chandrasetty
Springer Verlag, 2011
27*2011
Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes
VA Chandrasetty, SJ Johnson, G Lechner
IET Communications 8 (17), 3179-3188, 2014
26*2014
A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation
VA Chandrasetty, SM Aziz
Journal of Networks 7 (3), 441-449, 2012
182012
A reduced complexity message passing algorithm with improved performance for LDPC decoding
VA Chandrasetty, SM Aziz
Computers and Information Technology, 2009. ICCIT'09. 12th International …, 2009
122009
A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders
VA Chandrasetty, SM Aziz
Multimedia and Expo (ICME), 2011 IEEE International Conference on, 1-7, 2011
112011
Analysis of performance and implementation complexity of simplified algorithms for decoding low-density parity-check codes
VA Chandrasetty, SM Aziz
GLOBECOM Workshops (GC Wkshps), 2010 IEEE, 430-435, 2010
82010
A novel dual processing architecture for implementation of motion estimation unit of H. 264 AVC on FPGA
VA Chandrasetty, SR Laddha
Industrial Electronics & Applications, 2009. ISIEA 2009. IEEE Symposium on 1 …, 2009
52009
Construction of a multi-level Hierarchical Quasi-Cyclic matrix with layered permutation for partially-parallel LDPC decoders
VA Chandrasetty, SM Aziz
Computer and Information Technology (ICCIT), 2010 13th International …, 2010
42010
Resource efficient flexible architectures for low-density parity-check decoders
VA Chandrasetty
2012
High performance error correction codes for communication systems: research proposal
VA Chandrasetty
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