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Masanori Hariyama
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A low-power FPGA based on autonomous fine-grain power gating
S Ishihara, M Hariyama, M Kameyama
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (8 …, 2010
792010
OpenCL-based FPGA-platform for stencil computation and its optimization methodology
HM Waidyasooriya, Y Takei, S Tatsumi, M Hariyama
IEEE Transactions on Parallel and Distributed Systems 28 (5), 1390-1402, 2016
762016
VLSI processor for reliable stereo matching based on adaptive window-size selection
M Hariyama, T Takeuchi, M Kameyama
Proceedings 2001 ICRA. IEEE International Conference on Robotics and …, 2001
672001
FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture
M Hariyama, Y Kobayashi, H Sasaki, M Kameyama
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2005
602005
Design of FPGA-based computing systems with OpenCL
HM Waidyasooriya, M Hariyama, K Uchiyama
Springer International Publishing, 2018
472018
Evaluation of a field-programmable VLSI based on an asynchronous bit-serial architecture
M Hariyama, S Ishihara, M Kameyama
IEICE transactions on electronics 91 (9), 1419-1426, 2008
352008
Hardware-acceleration of short-read alignment based on the burrows-wheeler transform
HM Waidyasooriya, M Hariyama
IEEE Transactions on Parallel and Distributed Systems 27 (5), 1358-1372, 2015
322015
Asynchronous domino logic pipeline design based on constructed critical data path
Z Xia, M Hariyama, M Kameyama
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 619-630, 2014
302014
Reliable stereo matching for highly-safe intelligent vehicles and its VLSI implementation
M Hariyama, T Takeuchi, M Kameyama
Proceedings of the IEEE Intelligent Vehicles Symposium 2000 (Cat. No …, 2000
262000
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit
Z Xia, S Ishihara, M Hariyama, M Kameyama
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 3017-3020, 2012
252012
Multi-FPGA accelerator architecture for stencil computation exploiting spacial and temporal scalability
HM Waidyasooriya, M Hariyama
IEEE Access 7, 53188-53201, 2019
242019
A low-power field-programmable VLSI based on a fine-grained power-gating scheme
M Hariyama, S Ishihara, M Kameyama
2008 51st Midwest Symposium on Circuits and Systems, 702-705, 2008
242008
Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure
N Ohsawa, O Sakamoto, M Hariyama, M Kameyama
IEEE Computer Society Annual Symposium on VLSI, 258-259, 2004
242004
VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture
M Hariyama, M Kameyama
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004
232004
A collision detection processor for intelligent vehicles
M Hariyama, M Kameyama
IEICE Transactions on Electronics 76 (12), 1804-1811, 1993
231993
A field-programmable VLSI based on an asynchronous bit-serial architecture
M Hariyama, S Ishihara, CC Wei, M Kameyama
2007 IEEE Asian Solid-State Circuits Conference, 380-383, 2007
222007
Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access
M Hariyama, H Sasaki, M Kameyama
IEICE transactions on information and systems 88 (7), 1486-1491, 2005
212005
Architecture of a multi-context FPGA using reconfigurable context memory
W Chong, S Ogata, M Hariyama, M Kameyama
19th IEEE International Parallel and Distributed Processing Symposium, 7 pp., 2005
212005
Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltages
M Hariyama, T Aoyama, M Kameyama
IEEE transactions on computers 54 (6), 642-650, 2005
192005
Synchronising logic gates for wave-pipelining design
Z Xia, S Ishihara, M Hariyama, M Kameyama
Electronics letters 46 (16), 1116-1117, 2010
172010
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Articles 1–20