Steven Bentley
Steven Bentley
Adresse e-mail validée de globalfoundries.com
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Continuous flow in open microfluidics using controlled evaporation
M Zimmermann, S Bentley, H Schmid, P Hunziker, E Delamarche
Lab on a Chip 5 (12), 1355-1359, 2005
922005
Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts
JH Zhang, C Radens, SJ Bentley, BA Cohen, K Lim
US Patent 9,530,866, 2016
532016
Electron Mobility in Surface- and Buried-Channel FlatbandMOSFETs With ALDGate Dielectric
SJ Bentley, M Holland, X Li, GW Paterson, H Zhou, O Ignatova, ...
IEEE Electron Device Letters 32 (4), 494-496, 2011
472011
Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device
SJ Bentley, JH Zhang, K Lim, H Niimi
US Patent 9,640,636, 2017
432017
Self-aligned gate-first VFETs using a gate spacer recess
JH Zhang, K Lim, SJ Bentley, C Park
US Patent 9,536,793, 2017
392017
Methods of forming substrates comprised of different semiconductor materials and the resulting device
BJ Pawlak, S Bentley, A Jacob
US Patent 9,368,578, 2016
392016
Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process
BJ Pawlak, S Bentley, A Jacob
US Patent 8,716,156, 2014
372014
Methods of forming vertical transistor devices with self-aligned replacement gate structures
JH Zhang, C Radens, SJ Bentley, BA Cohen, K Lim
US Patent 9,530,863, 2016
322016
Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al2O3 formed by thermal oxidation of evaporated aluminium
S Taking, A Banerjee, H Zhou, X Li, AZ Khokhar, R Oxland, I McGregor, ...
Electronics letters 46 (4), 301-302, 2010
312010
Methods of forming epitaxial semiconductor material on source/drain regions of a finfet semiconductor device and the resulting devices
JA Fronheiser, BV Krishnan, MK Akarvardar, S Bentley, AP Jacob, J Liu
US Patent App. 14/164,934, 2015
232015
Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI
J Zhang, S Bentley, K Lim
US Patent 9,773,708, 2017
222017
Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
J Frougier, MG Sung, R Xie, C Park, S Bentley
US Patent 9,947,804, 2018
212018
Methods of forming a gate structure on a vertical transistor device
JH Zhang, SJ Bentley, K Lim
US Patent 9,799,751, 2017
172017
Method and structure to control channel length in vertical FET device
S Bentley, R Xie
US Patent 9,972,494, 2018
152018
Fabrication of 22 nm T-gates for HEMT applications
S Bentley, X Li, DAJ Moran, IG Thayne
Microelectronic engineering 85 (5-6), 1375-1378, 2008
142008
Multiple directed self-assembly material mask patterning for forming vertical nanowires
S Bentley, RA Farrell, G Schmid, AP Jacob
US Patent 10,186,577, 2019
132019
Method, apparatus and system for improved nanowire/nanosheet spacers
S Bentley, D Nayak
US Patent 9,748,335, 2017
132017
Two methods of realising 10 nm T-gate lithography
S Bentley, X Li, DAJ Moran, IG Thayne
Microelectronic engineering 86 (4-6), 1067-1070, 2009
132009
Junction overlap control in a semiconductor device using a sacrificial spacer layer
SJ Bentley, MJ Hargrove, C Chen, RO Jung, SK Kanakasabapathy, ...
US Patent 9,530,864, 2016
122016
Device isolation in finFET CMOS
AP Jacob, MK Akarvardar, SJ Bentley, T Nagumo, K Cheng, BB Doris, ...
US Patent 8,963,259, 2015
122015
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