Eric Schneider
Eric Schneider
University of Stuttgart, Institute of Computer Architecture and Computer Engineering
Adresse e-mail validée de iti.uni-stuttgart.de - Page d'accueil
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Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures
H Zhang, L Bauer, MA Kochte, E Schneider, C Braun, ME Imhof, ...
2013 IEEE International Test Conference (ITC), 1-10, 2013
372013
Test strategies for reliable runtime reconfigurable architectures
L Bauer, C Braun, ME Imhof, MA Kochte, E Schneider, H Zhang, J Henkel, ...
IEEE Transactions on Computers 62 (8), 1494-1507, 2013
282013
STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures
H Zhang, MA Kochte, E Schneider, L Bauer, HJ Wunderlich, J Henkel
Proceedings of the IEEE/ACM International Conference on Computer-Aided …, 2015
222015
GPU-accelerated small delay fault simulation
E Schneider, S Holst, MA Kochte, X Wen, HJ Wunderlich
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
202015
Scan test power simulation on GPGPUs
S Holst, E Schneider, HJ Wunderlich
2012 IEEE 21st Asian Test Symposium, 155-160, 2012
192012
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures
H Zhang, L Bauer, MA Kochte, E Schneider, HJ Wunderlich, J Henkel
IEEE Transactions on Computers 66 (6), 957-970, 2017
182017
GPU-Accelerated Simulation of Small Delay Faults
E Schneider, MA Kochte, S Holst, X Wen, HJ Wunderlich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
172017
Optimized selection of frequencies for faster-than-at-speed test
M Kampmann, MA Kochte, E Schneider, T Indlekofer, S Hellebrand, ...
2015 IEEE 24th Asian Test Symposium (ATS), 109-114, 2015
142015
Variation-aware deterministic ATPG
M Sauer, I Polian, ME Imhof, A Mumtaz, E Schneider, A Czutro, ...
2014 19th IEEE European Test Symposium (ETS), 1-6, 2014
112014
Data-parallel simulation for fast and accurate timing validation of CMOS circuits
E Schneider, S Holst, X Wen, HJ Wunderlich
Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided …, 2014
82014
High-Throughput Transistor-Level Fault Simulation on GPUs
E Schneider, HJ Wunderlich
2016 IEEE 25th Asian Test Symposium (ATS), 150-155, 2016
52016
Logic/clock-path-aware at-speed scan test generation for avoiding false capture failures and reducing clock stretch
K Asada, X Wen, S Holst, K Miyase, S Kajihara, MA Kochte, E Schneider, ...
2015 IEEE 24th Asian Test Symposium (ATS), 103-108, 2015
52015
Built-in Test for Hidden Delay Faults
M Kampmann, MA Kochte, C Liu, E Schneider, S Hellebrand, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
32018
Multi-level timing simulation on GPUs
E Schneider, MA Kochte, HJ Wunderlich
Proceedings of the 23rd Asia and South Pacific Design Automation Conference …, 2018
32018
Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors
S Holst, E Schneider, K Kawagoe, MA Kochte, K Miyase, HJ Wunderlich, ...
32017
Timing-Accurate Estimation of IR-Drop Impact on Logic-and Clock-Paths During At-Speed Scan Test
S Holst, E Schneider, X Wen, S Kajihara, Y Yamato, HJ Wunderlich, ...
2016 IEEE 25th Asian Test Symposium (ATS), 19-24, 2016
32016
SWIFT: Switch-Level Fault Simulation on GPUs
E Schneider, HJ Wunderlich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
12019
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
C Liu, E Schneider, M Kampmann, S Hellebrand, HJ Wunderlich
2018 IEEE 27th Asian Test Symposium (ATS), 92-97, 2018
12018
Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses
S Holst, E Schneider, MA Kochte, X Wen, HJ Wunderlich
2019 IEEE International Test Conference (ITC), 1-10, 2019
2019
Advances in hardware reliability of reconfigurable many-core embedded systems
L Bauer, H Zhang, MA Kochte, E Schneider, HJ Wunderlich, J Henkel
Many-Core Computing: Hardware and Software, 395, 2019
2019
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