Konstantinos Masselos
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System-level modeling of dynamically reconfigurable hardware with SystemC
A Pelkonen, K Masselos, M Cupák
Proceedings International Parallel and Distributed Processing Symposium, 8 pp., 2003
872003
Implementation and comparison of the 5/3 lifting 2D discrete wavelet transform computation schedules on FPGAs
ME Angelopoulou, K Masselos, PYK Cheung, Y Andreopoulos
Journal of signal processing systems 51 (1), 3-21, 2008
812008
System level design of reconfigurable systems-on-chip
NS Voros, K Masselos
Springer, 2005
57*2005
Strategy for power-efficient design of parallel systems
K Danckaert, K Masselos, F Cathoor, HJ De Man, C Goutis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (2), 258-265, 1999
541999
Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: A geometric programming framework
Q Liu, GA Constantinides, K Masselos, PYK Cheung
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
512009
Reconfigurability requirements of wireless communication systems
K Masselos, S Blionas, T Rautio
Proc. IEEE workshop on heterogeneous reconfigurable systems on chip, 2002
362002
Code transformations for embedded multimedia applications: impact on power and performance
ND Zervas, K Masselos, C Goutis
Proceedings of the Power-Driven Microarchitecture Workshop In Conjunction …, 1998
321998
Automatic on-chip memory minimization for data reuse
Q Liu, GA Constantinides, K Masselos, PYK Cheung
15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2007
312007
Outer loop pipelining for application specific datapaths in FPGAs
K Turkington, GA Constantinides, K Masselos, PYK Cheung
IEEE transactions on very large scale integration (VLSI) systems 16 (10 …, 2008
302008
High-level cache modeling for 2-D discrete wavelet transform implementations
Y Andreopoulos, P Schelkens, G Lafruit, K Masselos, J Cornelis
Journal of VLSI signal processing systems for signal, image and video …, 2003
302003
Data-reuse exploration for low-power realization of multimedia applications on embedded cores
ND Zervas, K Masselos, CE Goutis
Proc. of PATMOS 99, 71-80, 1999
241999
System-level modeling of dynamically reconfigurable co-processors
Y Qu, K Tiensyrjä, K Masselos
International Conference on Field Programmable Logic and Applications, 881-885, 2004
222004
FPGA based acceleration of the linpack benchmark: A high level code transformation approach
K Turkington, K Masselos, GA Constantinides, P Leong
2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006
202006
Implementation of wireless communications systems on FPGA-based platforms
K Masselos, NS Voros
EURASIP Journal on embedded systems 2007 (1), 012192, 2007
182007
Realization of wireless multimedia communication systems on reconfigurable platforms
K Masselos, A Pelkonen, M Cupak, S Blionas
Journal of systems architecture 49 (4-6), 155-175, 2003
182003
Compiling Scilab to high performance embedded multicore systems
T Stripf, O Oey, T Bruckschloegl, J Becker, G Rauwerda, K Sunesen, ...
Microprocessors and Microsystems 37 (8), 1033-1049, 2013
162013
A comparison of 2-D discrete wavelet transform computation schedules on FPGAs
M Angelopoulou, K Masselos, P Cheung, Y Andreopoulos
2006 IEEE International Conference on Field Programmable Technology, 181-188, 2006
162006
Data reuse exploration for FPGA based platforms applied to the full search motion estimation algorithm
Q Liu, K Masselos, GA Constantinides
2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006
152006
A novel algorithm for low-power image and video coding
K Masselos, P Merakos, T Stouraitis, CE Goutis
IEEE transactions on circuits and systems for video technology 8 (3), 258-263, 1998
151998
SystemC and OCAPI-xl based system-level design for reconfigurable systems-on-chip
K Tiensyrjä, M Cupak, K Masselos, M Pettissalo, K Potamianos, Y Qu, ...
Advances in Design and Specification Languages for SoCs, 255-269, 2005
142005
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