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S. M. Ali Zeinolabedin
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An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With W/Channel in 65-nm CMOS
AT Do, SMA Zeinolabedin, D Jeon, D Sylvester, TTH Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 126-137, 2018
362018
A 128-Channel Spike Sorting Processor Featuring 0.175 µW and 0.0033 mm2 per Channel in 65-nm CMOS
SMA Zeinolabedin, AT Do, D Jeon, D Sylvester, TH Kim
Symposium on VLSI Circuits, 2016
262016
A 16-Channel Fully Configurable Neural SoC With 1.52 W/Ch Signal Acquisition, 2.79 W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural …
SMA Zeinolabedin, FM Schüffny, R George, F Kelber, H Bauer, S Scholze, ...
IEEE Transactions on Biomedical Circuits and Systems 16 (1), 94-107, 2022
202022
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits
SMA Zeinolabedin, AT Do, KS Yeo, TTH Kim
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 794-797, 2015
102015
An area-and energy-efficient FIFO design using error-reduced data compression and near-threshold operation for image/video applications
SMA Zeinolabedin, J Zhou, X Liu, TTH Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2014
102014
Real-time hardware implementation of arm coresight trace decoder
SMA Zeinolabedin, J Partzsch, C Mayr
IEEE Design & Test 38 (1), 69-77, 2020
92020
Energy-efficient data-aware SRAM design utilizing column-based data encoding
AT Do, SMA Zeinolabedin, TTH Kim
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2154-2158, 2019
92019
Low computational complexity hardware implementation of Laplacian Pyramid
SMA Zeinolabedin, N Karimi, S Samavi
2010 18th Iranian Conference on Electrical Engineering, 465-470, 2010
82010
An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology
F Schüffny, S Höppner, S Hänzsche, RM George, SMA Zeinolabedin, ...
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021
62021
Analyzing ARM CoreSight ETMV4.X Data Trace Stream with a Real-Time Hardware Accelerator
SMA Zeinolabedin, J Partzsch, C Mayr
Design, Automation and Test in Europe Conference, 2021
52021
Contourlet based image compression using controlled modification of coefficients
N Karimi, S Samavi, S Shirani, H Talebi, SMA Zaynolabedin
2009 Canadian Conference on Electrical and Computer Engineering, 991-994, 2009
52009
A 0.3 PJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications
AT Do, SMA Zeinolabedin, TT Kim
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 173-176, 2016
42016
A 64-channel back-gate adapted ultra-low-voltage spike-aware neural recording front-end with on-chip lossless/near-lossless compression engine and 3.3 v stimulator in 22nm fdsoi
FM Schüffny, SMA Zeinolabedin, R George, L Guo, A Weiße, J Uhlig, ...
2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022
32022
An area-and power-efficient FIFO with error-reduced data compression for image/video processing
SMA Zeinolabedin, J Zhou, X Liu, TT Kim
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2277-2280, 2014
32014
A new quantization algorithm for fir filters coefficients
SMA Zeinolabedin, N Karimi
20th Iranian Conference on Electrical Engineering (ICEE2012), 1120-1124, 2012
32012
A Power and Area Efficient Ultra-low Voltage Laplacian Pyramid Processing Engine with Adaptive Data Compression
SMA Zeinolabedin, J Zhou, X Liu, TH Kim
IEEE Transactions on Circuits and Systems-I (TCAS-I), 2016
22016
A 0.5 V power and area efficient laplacian pyramid processing engine using FIFO with adaptive data compression
SMA Zeinolabedin, J Zhou, X Liu, TT Kim
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
22015
Various distance metrics evaluation on neural spike classification
S Guo, L Guo, SMA Zeinolabedin, C Mayr
2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), 554-558, 2022
12022
How to design an input stage for neural recording system in 22 nm FDSOI
FM Schuffny, S Höppner, SMA Zeinolabedin, RM George, C Mayr
2022 17th Conference on Ph. D Research in Microelectronics and Electronics …, 2022
12022
Structuring of Contourlet Transform for Pipeline-Based Implementation
SMA Zeinolabedin, N Karimi, S Samavi, TTH Kim
Circuits, Systems, and Signal Processing 35, 953-976, 2016
12016
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